5.4.29. SP810_SysCtrl component

The SP810_SysCtrl component is a programmer’s view model of the System Controller in the PrimeXsys® subsystem. For a detailed description of the behavior of the SP810, see other documentation. See the PrimeXsys System Controller (SP810) Technical Reference Manual.

Figure 5.51 shows a view of the component in System Canvas.

Figure 5.51. SP810_SysCtrl in System Canvas

SP810_SysCtrl in System Canvas

This component is written in LISA+.


Table 5.93 provides a brief description of the SP810_SysCtrl component ports. For more information, see the component documentation.

Table 5.93. SP810_SysCtrl ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder
clk_inClockSignalSlaveClock input
ref_clk_inClockSignalSlaveClock source used by the Timer and Watchdog modules
timer_clk_en[0]ClockRateControlMasterTimer clock enable 0
timer_clk_en[1]ClockRateControlMasterTimer clock enable 1
timer_clk_en[2]ClockRateControlMasterTimer clock enable 2
timer_clk_en[3]ClockRateControlMasterTimer clock enable 3
remap_clearStateSignalMasterRemap clear request output
npor[a]SignalSlavePower on reset
remap_stat[a]StateSignalSlaveRemap status input
sys_mode[a]ValueStateSlavePresent system mode
sys_stat[a]ValueStateSlaveSystem status input
wd_en[a]SignalSlaveWatchdog module enable input
hclkdivsel[a]ValueStateMasterDefine the processor clock/bus clock ratio
pll_en[a]SignalMasterPLL enable output
sleep_mode[a]SignalMasterControl clocks for SLEEP mode
wd_clk_en[a]SignalMasterWatchdog module clock enable output

[a] Not fully implemented. Using this port has unpredictable results.

Additional protocols

The SP810_SysCtrl component has no additional protocols.


Table 5.94 provides a description of the configuration parameters for the SP810_SysCtrl component.

Table 5.94. SP810_SysCtrl configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
sysidSystem identification registerInteger-0x00000000
use_s8Toggles whether switch S8 is enabledBooleantrue/falsefalse


Table 5.95 provides a description of the configuration registers for the SP810_SysCtrl component. See the component documentation for further details.

Table 5.95. SP810_SysCtrl registers

Register nameOffsetAccessDescription
SCCTRL0x0read/writeSystem control
SCSYSSTAT0x4read/writeSystem status
SCIMCTRL0x8read/writeInterrupt mode control
SCIMSTAT0xCread/writeInterrupt mode status
SCXTALCTRL0x10read/writeCrystal control
SCPLLCTRL0x14read/writePLL control
SCPLLFCTRL0x18read/writePLL frequency control
SCPERCTRL00x1Cread/writePeripheral control
SCPERCTRL10x20read/writePeripheral control
SCPEREN0x24write onlyPeripheral clock enable
SCPERDIS0x28write onlyPeripheral clock disable
SCPERCLKEN0x2Cread onlyPeripheral clock enable status
SCPERSTAT0x30read onlyPeripheral clock status
SCSysID00xEE0read onlySystem identification 0
SCSysID10xEE4read onlySystem identification 1
SCSysID20xEE8read onlySystem identification 2
SCSysID30xEECread onlySystem identification 3
SCITCR0xF00read/writeIntegration test control
SCITIR00xF04read/writeIntegration test input 0
SCITIR10xF08read/writeIntegration test input 1
SCITOR0xF0Cread/writeIntegration test output
SCCNTCTRL0xF10read/writeCounter test control
SCCNTDATA0xF14read/writeCounter data
SCCNTSTEP0xF18write onlyCounter step
SCPeriphID00xFE0read onlyPeripheral identification 0
SCPeriphID10xFE4read onlyPeripheral identification 1
SCPeriphID20xFE8read onlyPeripheral identification 2
SCPeriphID30xFECread onlyPeripheral identification 3
SPCellID00xFF0read onlyPrimeCell identification 0
SPCellID10xFF4read onlyPrimeCell identification 1
SPCellID20xFF8read onlyPrimeCell identification 2
SPCellID30xFFCread onlyPrimeCell identification 3

Debug features

The SP810_SysCtrl component has no debug features.

Verification and testing

The SP810_SysCtrl component has been tested as part of the Emulation Board model.


The SP810_SysCtrl component is not expected to significantly affect the performance of a PV system.

Library dependencies

The SP810_SysCtrl component has no dependencies on external libraries.

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