5.4.30. TZIC component

The TZIC component is a programmer’s view model of the TrustZone Interrupt Controller (TZIC) as described elsewhere. See AMBA 3 TrustZone Interrupt Controller (SP890) Revision: r0p0 Technical Overview (ARM DTO 0013).

The TZIC provides a software interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ and masks out the interrupt sources chosen for nFIQ from the interrupts that are passed onto a non-secure interrupt controller.

Figure 5.52 shows a view of the component in System Canvas.

Figure 5.52. TZIC in System Canvas

TZIC in System Canvas

This component is written in LISA+.


Table 5.96 provides a brief description of the ports. More details are in the Technical Overview. See the AMBA 3 TrustZone Interrupt Controller (SP890) Revision: r0p0 Technical Overview.

Table 5.96. TZIC ports

NamePort protocolTypeDescription
nsfiq_inSignalSlaveConnects to the nFIQ output of the non-secure interrupt controller
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder
sfiq_inSignalSlaveDaisy chaining secure FIQ input, otherwise connects to logic 1 if interrupt controller not daisy chained
input[32]SignalSlave32 interrupt input sources
fiq_outSignalMasterFIQ interrupt to processor
irq_out[32]SignalMaster32 IRQ output ports

Additional protocols

The TZIC component has no additional protocols.


The TZIC component has no parameters.


Table 5.97 provides a description of the configuration registers for the TZIC component.

Table 5.97. TZIC registers

Register nameOffsetAccessDescription
FIQStatus0x000read onlyProvide the status of the interrupts after FIQ masking.
RawIntr0x004read onlyProvide the status of the source interrupts and software interrupts to the interrupt controller.
IntSelect0x008read/writeSelect whether the corresponding input source can be used to generate an FIQ or whether it passes through to TZICIRQOUT.
FIQEnable0x00Cread/writeEnable the corresponding FIQ-selected input source, which can then generate an FIQ.
FIQEnClear0x010write onlyClear bits in the TZICFIQEnable register.
Bypass0x014read/writeEnable nNSFIQIN to be routed directly to FAQ, bypassing all TZIC logic. Only the least significant bit is used.
Protection0x018read/writeEnable or disable protected register access, stopping register accesses when the processor is in user mode.
Lock0x01Cwrite onlyEnable or disable all other register write access.
LockStatus0x020read onlyProvide the lock status of the TZIC registers.

Debug features

The TZIC component has no debug features.

Verification and testing

The TZIC component has been tested separately using its own test suite.

The SP890 TZIC component has been tested inside the SMLT component.

The FIQ has been tested under the secure environment.


The TZIC component is not expected to significantly affect the performance of a PV system.

Library dependencies

The TZIC component has no dependencies on external libraries.

Copyright © 2008-2013 ARM. All rights reserved.ARM DUI 0423O