5.4.22. PL330_DMAC component

The PL330_DMAC component is a programmer’s view model of the ARM PL330 Direct Memory Access Controller (DMAC). The DMA controller is modeled using a single LISA component but with a C++ model for each of the channels included in the LISA file. Enabled channels are kept on an enabled_channels stack in priority order. When a channel state changes, rearbitration takes place to make the highest (topmost) channel active. See the ARM PrimeCell DMA Controller (PL330) Technical Reference Manual.

Figure 5.44 shows a view of the component in System Canvas.

Figure 5.44. PL330_DMAC in System canvas

PL330_DMAC in System canvas

This component is written in LISA+.

Ports

Table 5.74 provides a brief description of the ports for the PL330_DMAC component. For more information, see the component documentation.

Table 5.74. PL330_DMAC ports

NamePort protocolTypeDescription
clk_inClockSignalSlaveMain processor clock input.
irq_abort_master_portSignalMasterUndefined instruction or instruction error.
irq_master_portSignalMasterSets when DMASEV.
pvbus_mPVBusMasterMaster port for all memory accesses.
pvbus_s_nsPVBusSlaveSlave port for all register accesses (non-secure).
reset_inSignalSlaveReset signal.

Additional protocols

The PL330_DMAC component has no additional protocols.

Parameters

Table 5.75 provides a description of the configuration parameters for the PL330_DMAC component.

Table 5.75. PL330_DMAC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
p_max_irqsNumber of interruptsInteger0-3232
p_max_channelsVirtual channelsInteger≤88
p_controller_nsecureController non-secure at resetBooleantrue or falsefalse
p_controller_bootsDMA boots from resetBooleantrue or falsetrue
p_reset_pcDMA PC at resetIntegerAny valid address0x60000000

Registers

Table 5.76 provides a description of the configuration registers for the PL330_DMAC component.

Table 5.76. PL330_DMAC registers

Register nameOffsetAccessDescription
DS0x000read onlyDMA status register
DPC0x004read onlyDMA program counter register
INTEN0x020read/writeInterrupt enable register
ES0x024read onlyEvent status register
INTSTATUS0x028read onlyInterrupt status register
INTCLR0x02cwrite onlyInterrupt clear register
FSM0x030read onlyFault status DMA manager register
FSC0x034read onlyFault status DMA channel register
FTM0x038read onlyFault type DMA manager register
FTC00x040read onlyFault type for DMA channel 0
FTC10x044read onlyFault type for DMA channel 1
FTC20x048read onlyFault type for DMA channel 2
FTC30x04cread onlyFault type for DMA channel 3
FTC40x050read onlyFault type for DMA channel 4
FTC50x054read onlyFault type for DMA channel 5
FTC60x058read onlyFault type for DMA channel 6
FTC70x05cread onlyFault type for DMA channel 7
CS00x100read onlyChannel status for DMA channel 0
CS10x108read onlyChannel status for DMA channel 1
CS20x110read onlyChannel status for DMA channel 2
CS30x118read onlyChannel status for DMA channel 3
CS40x120read onlyChannel status for DMA channel 4
CS50x128read onlyChannel status for DMA channel 5
CS60x130read onlyChannel status for DMA channel 6
CS70x138read onlyChannel status for DMA channel 7
CPC00x104read onlyChannel PC for DMA channel 0
CPC10x10cread onlyChannel PC for DMA channel 1
CPC20x114read onlyChannel PC for DMA channel 2
CPC30x11cread onlyChannel PC for DMA channel 3
CPC40x124read onlyChannel PC for DMA channel 4
CPC50x12cread onlyChannel PC for DMA channel 5
CPC60x134read onlyChannel PC for DMA channel 6
CPC70x13cread onlyChannel PC for DMA channel 7
SA_00x400read onlySource address for DMA channel 0
SA_10x420read onlySource address for DMA channel 1
SA_20x440read onlySource address for DMA channel 2
SA_30x460read onlySource address for DMA channel 3
SA_40x480read onlySource address for DMA channel 4
SA_50x4A0read onlySource address for DMA channel 5
SA_60x4C0read onlySource address for DMA channel 6
SA_70x4E0read onlySource address for DMA channel 7
DA_00x404read onlyDestination address for DMA channel 0
DA_10x424read onlyDestination address for DMA channel 1
DA_20x444read onlyDestination address for DMA channel 2
DA_30x464read onlyDestination address for DMA channel 3
DA_40x484read onlyDestination address for DMA channel 4
DA_50x4A4read onlyDestination address for DMA channel 5
DA_60x4C4read onlyDestination address for DMA channel 6
DA_70x4E4read onlyDestination address for DMA channel 7
CC_00x408read onlyChannel control for DMA channel 0
CC_10x428read onlyChannel control for DMA channel 1
CC_20x448read onlyChannel control for DMA channel 2
CC_30x468read onlyChannel control for DMA channel 3
CC_40x488read onlyChannel control for DMA channel 4
CC_50x4A8read onlyChannel control for DMA channel 5
CC_60x4C8read onlyChannel control for DMA channel 6
CC_70x4E8read onlyChannel control for DMA channel 7
LC0_00x40Cread onlyLoop counter for DMA channel 0
LC0_10x42Cread onlyLoop counter for DMA channel 1
LC0_20x44Cread onlyLoop counter for DMA channel 2
LC0_30x46Cread onlyLoop counter for DMA channel 3
LC0_40x48Cread onlyLoop counter for DMA channel 4
LC0_50x4ACread onlyLoop counter for DMA channel 5
LC0_60x4CCread onlyLoop counter for DMA channel 6
LC0_70x4ECread onlyLoop counter for DMA channel 7
LC1_00x410read onlyLoop counter 1 for DMA channel 0
LC1_10x430read onlyLoop counter 1 for DMA channel 1
LC1_20x450read onlyLoop counter 1 for DMA channel 2
LC1_30x470read onlyLoop counter 1 for DMA channel 3
LC1_40x490read onlyLoop counter 1 for DMA channel 4
LC1_50x4B0read onlyLoop counter 1 for DMA channel 5
LC1_60x4D0read onlyLoop counter 1 for DMA channel 6
LC1_70x4F0read onlyLoop counter 1 for DMA channel 7
DBGSTATUS0xD00read onlyDebug status register
DBGCMD0xD04write onlyDebug command register
DBGINST00xD08write onlyDebug instruction-0 register
DBGINST10xD0Cwrite onlyDebug instruction-1 register
periph_id_00xFE0read onlyPeripheral ID register 0
periph_id_10xFE4read onlyPeripheral ID register 1
periph_id_20xFE8read onlyPeripheral ID register 2
periph_id_30xFECread onlyPeripheral ID register 3
pcell_id_00xFF0read onlyPrimeCell ID register 0
pcell_id_10xFF4read onlyPrimeCell ID register 1
pcell_id_20xFF8read onlyPrimeCell ID register 2
pcell_id_30xFFCread onlyPrimeCell ID register 3

Debug features

The PL330_DMAC component has no debug features.

Verification and testing

The functions of the PL330_DMAC component have been tested individually using a tailored test suite.

Performance

The PL330_DMAC component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL330_DMAC component has no dependencies on external libraries.

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