5.4.17. PL111_CLCD component

The PL111_CLCD component provides all features of the programmer’s view model of the PL110 CLCD. The new hardware cursor feature of the PL111_CLCD is implemented as the major change compared with PL110.

The view of the component in System Canvas is shown in Figure 5.38.

Figure 5.38. PL111_CLCD in System Canvas

PL111_CLCD in System Canvas

This component is written in LISA+.


Table 5.61 provides a brief description of the ports. See also the ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual.

Table 5.61. PL111_CLCD ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
intrSignalMasterInterrupt signaling for flyback events.
clk_inClockSignalSlaveMaster clock input, typically 24MHz, to drive pixel clock timing.
displayLCDMasterConnection to visualization component. See Visualisation Library.
controlValueSlaveAuxiliary control register 1.
pvbus_mPVBusMasterDMA port for video data.

Additional protocols

The PL111_CLCD component has no additional protocols.


Table 5.62 provides a description of the configuration parameters for the PL111_CLCD component.

Table 5.62. PL111_CLCD configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
pixel_double_limitSets a threshold in horizontal pixels, below which pixels sent to the framebuffer are doubled in size horizontally and vertically.Integer-300


Table 5.63 provides a description of the configuration registers for the PL111_CLCD component.

Table 5.63. PL111_CLCD registers

Register nameOffsetAccessDescription
LCDTiming00x0read/writeHorizontal timing
LCDTiming10x4read/writeVertical timing
LCDTiming20x8read/writeClock and polarity control
LCDTiming30xCread/writeLine end control
LCDUPBASE 0x10read/writeUpper panel frame base address
LCDLPBASE0x14read/writeLower panel frame base address
LCDControl 0x18read/writeControl
LCDIMSC 0x1Cread/writeInterrupt mask
LCDRIS0x20read onlyRaw interrupt status
LCDMIS0x24read onlyMasked interrupt status
LCDICR0x28write onlyInterrupt clear
LCDIPCURR0x2Cread onlyUpper panel current address
LCDLPCURR0x30read onlyLower panel current address
LCDPalette0x200 - 0x3FCread/writePalette registers
CursorImage0x800-0xBFCread/writeCursor image RAM register
ClcdCrsCtrl0xC00read/writeCursor control
ClcdCrsrConfig0xC04read/writeCursor configuration
ClcdCrsrPalette00xC08read/writeCursor palette
ClcdCrsrPalette10xC0Cread/writeCursor palette
ClcdCrsrXY0XC10read/writeCursor XY position
ClcdCrsrClip0xC14read/writeCursor clip position
ClcdCrsrIMSC0xc20read/writeCursor interrupt mask set/clear
ClcdCrsrICR0xc24read/writeCursor interrupt clear
ClcdCrsrRIS0xc28read/writeCursor raw interrupt status
ClcdCrsrMIS0xc2cread/writeCursor masked interrupt status
CLCDPeriphID00xfe0readPeripheral ID register
CLCDPeriphID10xfe4readPeripheral ID register
CLCDPeriphID20xfe8readPeripheral ID register
CLCDPeriphID30xfecreadPeripheral ID register
CLCDPCellID00xff0readPrimeCell ID register
CLCDPCellID10xff4readPrimeCell ID register
CLCDPCellID20xff8readPrimeCell ID register
CLCDPCellID30xffcreadPrimeCell ID register

Debug features

The PL111_CLCD component has no debug features.

Verification and testing

The PL111_CLCD component has been tested as part of the PL111 test system using PL11x test suites.


The PL111_CLCD component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL111_CLCD component has no dependencies on external libraries.

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