A.1.6. Delayed operation of CP15 instructions

Rating: 2.

In general, the functional effect of any operation in the system control coprocessor, CP15 is not guaranteed to occur until after an Instruction Synchronization Barrier (ISB) is subsequently executed, or an exception entry or return occurs. There are several exceptions to this rule. Some guarantee earlier visibility in certain circumstances, and others require extra steps to guarantee that the operation takes place. These are described more fully in the ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition.

When parameter delayed_CP15_operations is set to true, the functional effects of the CP15 operations are postponed for as long as the model determines that it is legal to do so. That is, until the specified barrier is executed, or other ordering requirements force earlier completion.

Table A.1 shows the barrier type to be executed for the functional effect of specific cache and branch prediction operations to be seen in the model.

Table A.1. Delayed CP15 operations

CRnop1CRmop2OperationBarrier
c70c10Invalidate all instruction caches to PoU inner shareableDSB[a]
c70c16Invalidate entire branch predictor array inner shareableISB
c70c50Invalidate all instruction caches to PoU DSB[a]
c70c51Invalidate instruction caches by MVA to PoUDSB[a]
c70c54(Deprecated encoding) ISBImplicit
c70c56Invalidate entire branch predictor arrayISB
c70c57Invalidate MVA from branch predictorISB
c70c61Invalidate data cache line by MVA to PoCImplicit
c70c62Invalidate data cache line by set/wayDMB
c70c101Clean data cache line by MVA to PoCImplicit
c70c102Clean data cache line by set/wayDMB
c70c111Clean data cache line by MVA to PoUImplicit
c70c141Clean and invalidate data cache line by MVA to PoCImplicit
c70c142Clean and invalidate data cache line by set/wayDMB

[a] In general, an ISB would also be required in target code to guarantee that the following instruction fetch has not been pre-fetched from possibly stale data.


All other CP15 operations not listed in Table A.1 are postponed until an Instruction Synchronization Barrier (ISB) is executed or an exception entry or return occurs, subject to ordering requirements.

Where a Data Memory Barrier (DMB) is specified as the required barrier, a Data Synchronization Barrier (DSB) is a suitable alternative.

For more information on barrier requirements, see the sections relating to TLB maintenance, ordering of cache and branch predictor maintenance operations, and changes to CP15 registers and the memory order model in the ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition.

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