5.4.8. PL041_AACI component

The PL041_AACI component is a programmer’s view model of the PL041 Advanced Audio CODEC Interface (AACI). This component also contains a minimal register model of the LM4529 secondary codec as implemented on development boards supplied by ARM. For more information, see the component documentation. See the ARM PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual.

The PL041_AACI component is not a complete implementation of the AACI because the following functionality is not currently implemented:

The PL041_AACI component is designed to connect to an audio output component such as AudioOutFile or AudioOut_SDL. See AudioOut_File component. Also see AudioOut_SDL component.

Figure 5.29 shows a view of the component in System Canvas.

Figure 5.29. PL041_AACI in System Canvas

PL041_AACI in System Canvas

This component is written in LISA+.


Table 5.44 provides a brief description of the ports on the PL041_AACI component. For more information, see the component documentation.

Table 5.44. PL041_AACI ports

NamePort protocolTypeDescription
clk_ref_inClockSignalSlaveReference clock input, typically 25MHz.
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
audioAudioControlMasterUsed to communicate with an audio out device.
irqSignalMasterSingle IRQ output port.

AudioControl protocol

The PL041_AACI component has one additional protocol.

The AudioControl protocol has the following behaviors:


get an underlying host buffer for audio output


release an underlying host buffer.


The PL041_AACI component has no parameters.


Table 5.45 provides a description of the registers for the PL041_AACI component.

Table 5.45. PL041_AACI registers

Register nameOffsetAccessDescription
RXCR10x00read/writeFIFO1 receive control
TXCR10x04read/writeFIFO1 transmit control
SR10x08read/writeChannel 1 status
ISR10x0Cread/writeChannel 1 interrupt status
IE10x10read/writeChannel 1 interrupt enable
RXCR20x14read/writeFIFO2 receive control
TXCR20x18read/writeFIFO2 transmit control
SR20x1Cread/writeChannel 2 status
ISR20x20read/writeChannel 2 interrupt status
IE20x24read/writeChannel 2 interrupt enable
RXCR30x28read/writeFIFO3 receive control
TXCR30x2Cread/writeFIFO3 transmit control
SR30x30read/writeChannel 3 status
ISR30x34read/writeChannel 3 interrupt status
IE30x38read/writeChannel 3 interrupt enable
RXCR40x3Cread/writeFIFO4 receive control
TXCR40x40read/writeFIFO4 transmit control
SR40x44read/writeChannel 4 status
ISR40x48read/writeChannel 4 interrupt status
IE40x4Cread/writeChannel 4 interrupt enable
SL1RX0x50read/writeSlot 1 receive data
SL1TX0x54read/writeSlot 1 transmit data
SL2RX0x58read/writeSlot 2 receive data
SL2TX0x5Cread/writeSlot 2 transmit data
SL12RX0x60read/writeSlot 12 receive data
SL12TX0x64read/writeSlot 12 transmit data
LSFR0x68read/writeSlot flag register
SLISTAT0x6Cread/writeSlot interrupt status
SLIEN0x70read/writeSlot interrupt enable
ALLINTCLR0x74write onlyAll interrupts clear
MAINCR0x78read/writeMain control
RESET0x7Cread/writeReset control
SYNC0x80read/writeSync control
ALLINTS0x84read/writeAll FIFO interrupts status
MAINFR0x88read/writeMain flags register

Debug features

The PL041_AACI component has no debug features.

Verification and testing

The PL041_AACI component has been tested using the ALSA driver for this component under Linux.


The PL041_AACI component relies on a timed callback from the simulation so might have a small impact on simulation performance. The ability to play audio through this component depends on the AudioOut Component in use and on the performance requirements of the software running on the simulated system. The rate of FIFO draining is controlled by the audio output to which the component is connected. This might not correspond to the rate that would be expected from the reference clock.

Library dependencies

The PL041_AACI component has no dependencies on external libraries.

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