5.4.15. PL080_DMAC component

The PL080_DMAC component is a programmer’s view model of the ARM PL080 DMA Controller. It provides eight configurable DMA channels, and 16 DMA ports for handshaking with peripherals. You can configure each channel to operate in one of eight flow control modes either under DMA control or the control of the source or destination peripheral. Transfers can occur on either master channel and can optionally be endian converted on both source and destination transfers. See external documentation for additional details on the PL080. See the ARM PrimeCell DMA Controller (PL080) Technical Reference Manual.

Figure 5.36 shows a view of the component in System Canvas.

Figure 5.36. PL080_DMAC in System Canvas

PL080_DMAC in System Canvas

This component is written in LISA+.

Ports

Table 5.55 provides a brief description of the ports in the PL080_DMAC component. For more information, see the component documentation.

Table 5.55. PL080_DMAC ports

NamePort protocolTypeDescription
pvbus_sPVBusSlaveSlave bus for register accesses
clk_inClockSignalSlaveClock signal to control DMA transfer rate
reset_inSignalSlaveReset signal
pvbus0_mPVBusMasterMaster bus interface 0 for DMA transfers
pvbus1_mPVBusMasterMaster bus interface 1 for DMA transfers
interrSignalMasterDMA error interrupt signal
inttcSignalMasterDMA terminal count signal
intrSignalMasterCombined DMA error and terminal count signal
dma_port[16]PL080_DMAC_DmaPortProtocol[a]SlavePeripheral handshake ports

PL080_DMAC_DmaPortProtocol

The PL080_DMAC component has one additional protocol.

The PL080_DMAC_DmaPortProtocol protocol provides methods to permit handshaking between peripherals and the DMA controller.

request(uint32 request) : void

Passes requests from a peripheral to the DMA controller. The request is a bitfield with the low four bits defined. The request is level sensitive and latched internally by the DMA controller. It is sampled and interpreted in a manner dependent on the target channel and configured flow control.

0: PL080_REQ_BURST

burst transfer request

1: PL080_REQ_SINGLE

single transfer request

2: PL080_REQ_LBURST

last burst request

3: PL080_REQ_LSINGLE

last single request.

response(uint32 response) : void

Passes responses from the DMA controller to peripherals. The response is a bitfield with the low two bits defined. The response is transient rather than level sensitive.

0: PL080_RES_TC

terminal count response

1: PL080_RES_CLR

clear request response.

Parameters

Table 5.56 provides a description of the configuration parameters for the PL080_DMAC component.

Table 5.56. PL080_DMAC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
fifo_sizeControls the size of channel FIFOs in bytesInteger0-102416
max_transferLimits the number of transfers that can be made atomicallyInteger1-1024256
generate_clearControls whether completion of a burst/single transfer generates a clear response to peripheralsBooleantrue/falsefalse
activate_delaySets the minimum number of cycles after a request or channel enableInteger0-2560

Registers

Table 5.57 provides a description of the configuration registers for the PL080_DMAC component.

Table 5.57. PL080_DMAC registers

Register nameOffsetAccessDescription
IrqStatus0x000read onlyCombined interrupt status
IrqTCStatus0x004read onlyMasked terminal count status
IrqTCClear0x008write onlyTerminal count clear
IrqErrStatus0x00Cread onlyMasked error status
IrqErrClear0x010write onlyError clear
RawIrqTCStatus0x014read onlyRaw terminal count status
RawIrqErrStatus0x018read onlyRaw error status
EnabledChannels0x01Cread onlyEnabled channels
SoftBReq0x020read/writeSoft burst request/status
SoftSReq0x024read/writeSoft single request/status
SoftLBReq0x028read/writeSoft last burst request/status
SoftLSReq0x02Cread/writeSoft last single request/status
Configuration0x030read/writeMaster configuration
Sync0x034read/writeSynchronization control
C0SrcAddr0x100read/writeChannel source address
C0DstAddr0x104read/writeChannel destination address
C0LLI0x108read/writeChannel linked list item
C0Control0x10Cread/writeChannel control
C0Config0x110read/writeChannel configuration
C1SrcAddr0x120read/writeChannel source address
C1DstAddr0x124read/writeChannel destination address
C1LLI0x128read/writeChannel linked list item
C1Control0x12Cread/writeChannel control
C1Config0x130read/writeChannel configuration
C2SrcAddr0x140read/writeChannel source address
C2DstAddr0x144read/writeChannel destination address
C2LLI0x148read/writeChannel linked list item
C2Control0x14Cread/writeChannel control
C2Config0x150read/writeChannel configuration
C3SrcAddr0x160read/writeChannel source address
C3DstAddr0x164read/writeChannel destination address
C3LLI0x168read/writeChannel linked list item
C3Control0x16Cread/writeChannel control
C3Config0x170read/writeChannel configuration
C4SrcAddr0x180read/writeChannel source address
C4DstAddr0x184read/writeChannel destination address
C4LLI0x188read/writeChannel linked list item
C4Control0x18Cread/writeChannel control
C4Config0x190read/writeChannel configuration
C5SrcAddr0x1A0read/writeChannel source address
C5DstAddr0x1A4read/writeChannel destination address
C5LLI0x1A8read/writeChannel linked list item
C5Control0x1ACread/writeChannel control
C5Config0x1B0read/writeChannel configuration
C6SrcAddr0x1C0read/writeChannel source address
C6DstAddr0x1C4read/writeChannel destination address
C6LLI0x1C8read/writeChannel linked list item
C6Control0x1CCread/writeChannel control
C6Config0x1D0read/writeChannel configuration
C7SrcAddr0x1E0read/writeChannel source address
C7DstAddr0x1E4read/writeChannel destination address
C7LLI0x1E8read/writeChannel linked list item
C7Control0x1ECread/writeChannel control
C7Config0x1F0read/writeChannel configuration
PeriphID00xFE0read onlyPrimeCell peripheral ID
PeriphID10xFE4read onlyPrimeCell peripheral ID
PeriphID20xFE8read onlyPrimeCell peripheral ID
PeriphID30xFECread onlyPrimeCell peripheral ID
PCellID00xFF0read onlyPrimeCell ID
PCellID10xFF4read onlyPrimeCell ID
PCellID20xFF8read onlyPrimeCell ID
PCellID30xFFCread onlyPrimeCell ID

Debug features

The PL080_DMAC component has no debug features.

Verification and testing

The functions of the PL080_DMAC component have been tested individually using a tailored test suite.

Performance

The PL080_DMAC component might have a significant impact on system performance in certain flow control modes. Channels configured for small bursts, or using single bursts, and with peripheral DMA handshaking could add significant overheads. The peripheral has not been fully optimized to make use of the advanced features of the PVBus model.

Library dependencies

The PL080_DMAC component has no dependencies on external libraries.

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