5.4.41. IntelStrataFlashJ3 component

The IntelStrataFlashJ3 component provides an efficient implementation of a NOR Flash memory type device. In normal usage, the device acts as Read Only Memory (ROM) whose contents can be determined either by programming using the flashloader port or by using standard flash programming software run on the model, such as the ARM Firmware Suite.

The size of the flash is determined by a startup parameter, size.

The IntelStrataFlashJ3 component implementation is approximately that of the Intel part used in the VE development board. The component is effectively organized as a bank of two 16bit Intel Flash components forming a 32bit component that can be read or programmed in parallel. The component supports all hardware behavior except for the following:

All block operations are atomic. This means that the status register state machine status bit always reads 1, ready.

For further information on the behavior of the hardware, see the Intel datasheet for the Intel StrataFlash Memory (J3). See Download Center.

Figure 5.63 shows a view of the component in System Canvas.

Figure 5.63. IntelStrataFlashJ3 in System Canvas

IntelStrataFlashJ3 in System Canvas

This component is written in LISA+.

Ports

Table 5.117 provides a brief description of the IntelStrataFlashJ3 component ports.

Table 5.117. IntelStrataFlashJ3 ports

NamePort protocolTypeDescription
flashloaderFlashLoaderPortSlavePermits a FlashLoader component to initialize the flash contents from a binary file
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder
mbs_controlPVBusSlaveControlMasterInternal control
mem_portPVDeviceSlave 

Additional protocols

The IntelStrataFlashJ3 component has one additional protocol, FlashLoaderPort. See FlashLoaderPort.

Parameters

Table 5.118 lists the parameters for the IntelStrataFlashJ3 component.

Table 5.118. IntelStrataFlashJ3 configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
sizeSet the size of the component in bytesIntegermust be a power of 264MB

Registers

In normal operation the IntelStrataFlashJ3 component has no user visible registers. The device responds to the Common Flash Interface protocol which permits the device to be programmed at runtime. See general flash programming documentation on how to use the interface.

Debug features

The IntelStrataFlashJ3 component can be read/written using normal debugWrites.

Verification and testing

The IntelStrataFlashJ3 component has been tested as part of the VE example system using VE test suites and by booting operating systems.

Performance

The IntelStrataFlashJ3 component is not expected to significantly affect the performance of a PV system.

Library dependencies

The IntelStrataFlashJ3 component has no dependencies on external libraries.

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