4.21. CADI interactions with processor behavior

M-series processors are architecturally defined to have different reset behavior to that of A and R series processors.

For all processors, that is, in hardware and in the models, a reset consists of asserting, and then deasserting the reset pin. However:

The behavior of reset on M series interacts differently with CADI debugging functionality than it does for A and R series. On A and R series, after the reset pin of the processor is asserted, a new application can be loaded using CADIExecLoadApplication() call in CADI. This loads an application into memory, and sets the PC if a start address is specified in the application. When reset is deasserted, the processor begins fetching and executing from the start address as expected. Similarly, if a debugger asserts reset on the processor, it can modify memory with a sequence of CADIMemWrite() calls, update the PC with a CADIRegWrite() call, and when reset is deasserted the processor will begin fetching and executing from PC.

On M series processors the above techniques do not normally work, because the processor updates SP_main and the PC after reset is deasserted, and so overwrites the SP_main and PC set by the CADI calls.

To make it possible for these techniques to be used, the M series processor models differ slightly from the architectural reset behavior. When reset is asserted, the M series makes note of whether the PC or SP are modified before reset is next deasserted. If there are any CADI writes to the PC or SP registers, either directly through CADIRegWrite or indirectly through CADIExecLoadApplication(), this is tracked. When reset is deasserted, if the PC has been modified using CADI, the PC retains the value written to it, otherwise it reads it from address VTOR+0. Similarly, if the SP has been modified using CADI, SP_main retains the value written to it, otherwise it reads it from address VTOR+4.

Copyright © 2008-2013 ARM. All rights reserved.ARM DUI 0423O
Non-ConfidentialID060613