A.1.10. Other checks

The checks that are described in this section are always enabled. You can, however, suppress any message from being printed by adjusting the corresponding severity level parameter. See Message configuration.

Exclusive access into non-normal memory

LDREX, STREX and similar instructions are only guaranteed to operate correctly in normal memory. Their operation in other memory types such as Device or Strongly Ordered, is not architecturally defined and must not be relied on. For example, some implementations take an external abort.

BX or BLX to illegal addresses

An address ending 0b10 is not a legal branch target.

Non-normal pagetables should have XN bit set

The ARM architecture does not guarantee that a processor executes instructions from non-normal memory types such as Device or Strongly Ordered. Some implementations can take a pre-fetch abort. It is recommended that the XN bit is set in pagetables for non-normal memory to avoid seeing IMPLEMENTATION DEFINED effects in executed code.

Assumptions about cache geometry

Cache maintenance operations can be indexed by set and way. Any program that uses these operations must have read the cache ID registers to determine the number of sets and ways present in the system. Compatibility is not guaranteed if the target code attempts to infer this information from reading the Main ID register.

Overlapping pagetable entries

It is an error if the TLB is permitted to contain more than one physical address mapping for each combination of virtual address, Application Space Identifier (ASID) and security state. This might occur if entries in the TLB are not flushed before loading a different set of pagetables describing regions of a different size, or if pagetable entries are not correctly repeated for a Supersection or Large Page entry.

Pagetable properties remapped whilst MMU is enabled

The status of System Control Register bits EE, AFE and TRE affect the way that pagetables are interpreted, but it is IMPLEMENTATION DEFINED whether the interpretation takes place when the TLB is loaded or when it is used. Therefore, if these bits are changed while there are active TLB entries, any entries currently in the TLB might not be correctly interpreted.

AP==110 deprecated

Pagetable entries using the encoding AP[2] = 1, AP[1:0] = 0b10 means read-only for both privileged mode and user mode accesses, but its use is deprecated in VMSAv7. Instead use AP[2] = 1, AP[1:0] = 0b11.

A dirty cache line was invalidated but not cleaned

When the invalidate cache maintenance operation is performed on a writeback cache, the data in any dirty lines might or might not have been flushed to the next cache level or backing RAM. Any subsequent data reads from that address are therefore ambiguous. It is legal to do this, but take care that it is not used improperly or else bugs can be introduced.

Reserved encoding

When extended addressing is in use, each 8-bit field of the MAIR0 and MAIR1 registers must be written with a valid memory type. Writing any field with values of the following form is unpredictable:

  • 0xyy xxxx for values of yy other than 0

  • xxxx 0xyy for values of yy other than 0

  • yyyy 0000 for values of yyyy other than 0

  • 0000 1xxx.

Incoherency between S and NS memory

Some system platforms (such as the VE) do not distinguish between SECURE and NON_SECURE memory accesses, and the storage destination depends only on the physical address regardless of the NS bit. In these cases, using S and NS versions of the same physical address can have unpredictable cache incoherency effects. For example, if the cache contains dirty lines for the same address in each state, the final memory contents depend on random eviction order.

When the AEM, however, is used as a component in a system platform that distinguishes between S and NS accesses, this usage is perfectly legal and recommended, so this warning must be disabled by decreasing the value of the messages.severity_level_E_ReservedEncoding parameter.

Exception level change

Various unpredictable effects can occur if an MSR or CPS instruction is used to change privilege level, for example, leaving monitor mode with SCR.NS==0, leaving hyp mode, or entering user mode.

In preference, target code must use one of the exception return operations such as RFE, ERET or SUBS PC, LR.

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