5.4.18. PL180_MCI component

The PL180_MCI component provides a programmer’s view model of the PL180 Multimedia Card Interface (MCI). See the ARM PrimeCell Multimedia Card Interface (PL180) Technical Reference Manual.

When paired with an MMC card model, the PL180_MCI component provides emulation of a flexible, persistent storage mechanism. The PL180_MMC component fully models the registers of the corresponding PrimeCell, but supports a subset of the functionality of the PL180. Specifically:

The view of the component in System Canvas is shown in Figure 5.39.

Figure 5.39. PL180_MCI in System Canvas

PL180_MCI in System Canvas

This component is written in LISA+.


Table 5.64 provides a brief description of the ports.

Table 5.64. PL180_MCI ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
MCIINTR[0-1]SignalMasterInterrupt request ports.
mmc_mMMC_ProtocolMasterThe Multi Media Card (MMC) master port.


The PL180_MCI component has one additional protocol.

MMC_Protocol describes an abstract, untimed interface between an MMC controller and an MMC or SD card. The protocol contains a number of methods that must be implemented by the master (controller) and some that must be implemented by the slave (card). This protocol is used by the reference PL180 MCI and MMC models. Further information on the protocol implementation can be found in the source file. See %PVLIB_HOME%\LISA\MMC_Protocol.lisa.

Use of this protocol assumes some knowledge of the MultiMediaCard specification, available from the MultiMediaCard Association, www.mmca.org.

MMC_Protocol has the following behaviors:


Commands are sent from the controller to the card using this behavior, which is implemented by the card model. The MMC command is sent with an optional argument. The card responds as defined by the MMC specification. The controller model checks that the response type matches expectations, and updates its state appropriately. The transaction-level protocol does not model start/stop bits or CRCs on the command/response payload.

For data transfer in the card to controller direction, the behaviors are:


After the host and controller have initiated a read through the command interface, the card calls the Rx behavior on the controller to provide the read data. The call provides a pointer and a length. The ARM MMC reference model simulates device read latency by waiting a number of clock cycles prior to calling this behavior. If the controller is unable to accept the data, or wants to force a protocol error, it can return false in response to this behavior.


A handshake, used by the controller to inform the card that the controller is ready to receive more data. The ARM MMC reference model does not time out, so waits indefinitely for this handshake in a multiple block data transfer.

For data transfer in the controller to card direction, the behaviors are:


After the host and controller have initiated a write through the command interface, the card calls the Tx behavior on the controller. The call provides a pointer to an empty buffer to be written, and a length. The ARM MMC reference model simulates device write latency by waiting a number of clock cycles prior to each buffer being offered.


The controller calls this behavior on the card when the block has been written. The card model can then commit the data to its persistent storage.

The card model must also implement:


This behavior returns the name of the command issued. A card must implement this behavior, but is free to return an empty string for all requests. Only call this behavior for diagnostic messages.


The PL180_MCI component has no parameters.


Table 5.65 provides a description of the configuration registers for the PL180_MCI component.

Table 5.65. PL180_MCI registers

Register nameOffsetAccessDescription
MCIPower0x000read/writePower control register
MCIClock0x004read/writeClock control register
MCIArgument0x008read/writeArgument register
MCICommand0x00Cread/writeCommand register
MCIRespCmd0x010read onlyResponse command register
MCIResponse00x014read onlyResponse register
MCIResponse10x018read onlyresponse registerR
MCIResponse20x01Cread onlyResponse register
MCIResponse30x020read onlyResponse register
MCIDataTimer0x024read/writeData timer
MCIDataLength0x028read/writeData length register
MCIDataCtrl0x02Cread/writeData control register
MCIDataCnt0x030read onlyData counter
MCIStatus0x034read onlyStatus register
MCIClear0x038write onlyClear register
MCIMask00x03Cread/writeInterrupt 0 mask register
MCIMask10x040read/writeInterrupt 1 mask register
MCISelect0x044read/writeSecure Digital card select register
MCIFifoCnt0x048read onlyFIFO counter
MCIFIFO0x080read/writedata FIFO register
MCIPeriphID00xFE0read onlyPeripheral ID bits 7:0
MCIPeriphID10xFE4read onlyPeripheral ID bits 15:8
MCIPeriphID20xFE8read onlyPeripheral ID bits 23:16
MCIPeriphID30xFECread onlyPeripheral ID bits 31:24
MCIPCellID00xFF0read onlyPrimeCell ID bits 7:0
MCIPCellID10xFF4read onlyPrimeCell ID bits 15:8
MCIPCellID20xFF8read onlyPrimeCell ID bits 23:16
MCIPCellID30xFFCread onlyPrimeCell ID bits 31:24

Debug features

At compile time, command tracing can be enabled within the PL180_MCI component by modifying the PL180_TRACE macro in the MMC.lisa file. This sends command and event trace to standard output. You can use this output to help diagnose device driver and controller-to-card protocol issues.

Verification and testing

The PL180_MCI component has been tested in conjunction with the ARM MMC reference model. The component has been tested in the VE example with Boot Monitor and Linux drivers.


The PL180_MCI component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL180_MCI component has no dependencies on external libraries.

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