5.4.36. AndGate component

The AndGate component implements a logical AND of two Signal input ports to generate a single output Signal. You can use this, for example, to combine two interrupt signals.

Figure 5.58 shows a view of the component in System Canvas.

Figure 5.58. AndGate in System Canvas

AndGate in System Canvas

This component is written in LISA+.

Ports

Table 5.108 provides a brief description of the AndGate component ports.

Table 5.108. AndGate ports

NamePort protocolTypeDescription
input[0]SignalSlaveFirst input signal
input[1]SignalSlaveSecond input signal
outputSignalMasterCombined output signal

Additional protocols

The AndGate component has no additional protocols.

Parameters

The AndGate component has no parameters.

Registers

The AndGate component has no registers.

Debug features

The AndGate component has no debug features.

Verification and testing

The AndGate component has been tested as part of the VE example system using VE test suites and by booting operating systems.

Performance

The AndGate component is not expected to significantly affect the performance of a PV system.

Library dependencies

The AndGate component has no dependencies on external libraries.

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