5.4.31. TZMPU component

The TZMPU component is a programmer’s view model of the TrustZone Memory Protection Unit (TZMPU). The TZMPU has been superseded by the TrustZone Address Space Controller (TZASC), so other documentation on the component is limited to internal specifications.

The TZMPU component is conceptualized as an address filter. You can program a configurable number of regions to grant different access rights for secure and non-secure AXI transactions to different areas of memory.

Figure 5.53 shows a view of the component in System Canvas.

Figure 5.53. TZMPU in System Canvas

TZMPU in System Canvas

This component is written in LISA+.

Ports

Table 5.98 provides a brief description of the ports.

Table 5.98. TZMPU ports

NamePort protocolTypeDescription
apb_sPVBusSlaveAPB slave port
axi_sPVBusSlaveAXI slave port
axi_mPVBusMasterAXI master port
interruptSignalMasterInterrupt signalling port

Additional protocols

The TZMPU component has no additional protocols.

Parameters

Table 5.99 provides a description of the configuration parameters for the TZMPU component.

Table 5.99. TZMPU configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
numRegionsNumber of memory regionsInteger2 to 16, in increments of 116
axiAddrWidthAXI address width, in bitsInteger32 to 64, in increments of 1 bit32

Registers

Table 5.100 provides a description of the configuration registers for the TZMPU component.

Table 5.100. TZMPU registers

Register nameOffsetAccessDescription
configuration0x000read onlyDefines AXI address width and number of regions.
action0x004read/writeAction for access permission failures.
lockdown_range0x008read/writeRegion lockdown range.
lockdown_enable0x00Cread/writeRegion lockdown select.
int_status0x010read onlyIndicates status of permission failures.
int_clear0x014write onlyClear unserviced interrupts.
fail_address_low0x020read onlyLow order 32 bits of address failed.
fail_address_high0x024read onlyHigh order 32 bits of address failed.
fail_control0x028read onlyAccess type of failed accesses.
fail_id0x02Cread onlyMaster AXI ID of failed access.
region_base_lo_00x100read only, or read/write[a]Protection region 0 base low address.
region_base_hi_00x104read only, or read/write[a]Protection region 0 base high address.
region_attr_sz_00x108read only, or read/write[a]Protection region 0 size.
region_base_lo_10x110read only, or read/write[a]Protection region 1 base low address.
region_base_hi_10x114read only, or read/write[a]Protection region 1 base high address.
region_attr_sz_10x118read only, or read/write[a]Protection region 1 size.
region_base_lo_150x1F0read only, or read/write[a]Protection region 15 base low address.
region_base_hi_150x1F4read only, or read/write[a]Protection region 15 base high address.
region_attr_sz_150x1F8read only, or read/write[a]Protection region 15 size.
itcr0xE00read/writeIntegration test control register.
itip0xE04read onlyIntegration test input register.
itop0xE08read/writeIntegration test output register.
periph_id_00xFE0read onlyPeripheral identification register.
periph_id_10xFE4read onlyPeripheral identification register.
periph_id_20xFE8read onlyPeripheral identification register.
periph_id_30xFECread onlyPeripheral identification register.
pcell_id_00xFF0read onlyPrimeCell identification register 0.
pcell_id_10xFF4read onlyPrimeCell identification register 1.
pcell_id_20xFF8read onlyPrimeCell identification register 2.
pcell_id_30xFFCread onlyPrimeCell identification register 3.

[a] Regions specified in the lockdown_range register are locked down and are read only, otherwise they are read/write.


Debug features

The TZMPU component has no debug features.

Verification and testing

The TZMPU component has been tested separately using its own test suite.

Performance

The TZMPU component is not expected to significantly affect the performance of a PV system.

Library dependencies

The TZMPU component has no dependencies on external libraries.

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