A.1.3. Infinite write buffer

Rating: 4.

When the parameter vmsa.infinite_write_buffer is set, write accesses performed by one processor are not visible to other processors, or outside the processor, unless a relevant barrier operation is performed or until a sufficiently long elapsed delay has occurred.

You can adjust the delay time with the parameter vmsa.write_buffer_delay, which is the approximate number of instructions between successive buffer drains. If you set this parameter to 0, then no time-based drains occur, and you must perform explicit barrier operations.

In regions marked as Device or Strongly Ordered memory, accesses complete in an order relative to other accesses of the same type, but can be interleaved with accesses to Normal memory. Writes to these regions are not combinable, and reads cannot be satisfied from the buffer, so an explicit read access invokes the completion of all pending write accesses to that memory type.

You can use this feature most effectively with the cache incoherence check. See Cache incoherence check.

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