5.4.26. PL390_GIC component

The PL390 is a Generic Interrupt Controller (GIC) which implements the ARM Generic Interrupt Controller Architecture. The component is based on r0p0 of the PL390 Interrupt Controller.

The GIC provides support for three interrupt types:

Interrupts are programmable so that the following can be set:

For a detailed description of the behavior of the PL390 Interrupt Controller, see the component documentation. See ARM PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual and the Generic Interrupt Controller Architecture Specification.

Figure 5.41 shows a view of the component in System Canvas.

Figure 5.48. PL390_GIC in System Canvas

PL390_GIC in System Canvas

This component is written in LISA+ and C++.

Ports

Table 5.85 provides a brief description of the PL390_GIC component ports. For more information, see the component documentation.

Table 5.85. PL390_GIC ports

NamePort protocolTypeDescription
nfiq [8]SignalMasterSend out FIQ signal to processor <n>
nirq [8]SignalMasterSend out IRQ signal to processor <n>
ppi_c0 [16]SignalSlavePrivate peripheral interrupt for processor 0 (num_cpus>=1)
ppi_c1 [16]SignalSlavePrivate peripheral interrupt for processor 1 (num_cpus>=2)
ppi_c2 [16]SignalSlavePrivate peripheral interrupt for processor 2 (num_cpus>=3)
ppi_c3 [16]SignalSlavePrivate peripheral interrupt for processor 3 (num_cpus>=4)
ppi_c4 [16]SignalSlavePrivate peripheral interrupt for processor 4 (num_cpus>=5)
ppi_c5 [16]SignalSlavePrivate peripheral interrupt for processor 5 (num_cpus>=6)
ppi_c6 [16]SignalSlavePrivate peripheral interrupt for processor 6 (num_cpus>=7)
ppi_c7 [16]SignalSlavePrivate peripheral interrupt for processor 7 (num_cpus>=8)
pvbus_cpuPVBusSlaveSlave port for connection to processor interface
pvbus_distributorPVBusSlaveSlave port for connection to distributor interface
enable_c [8]ValueSlaveCompared with masked PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>
match_c [8]ValueSlaveMask on the PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>
enable_d [8]ValueSlaveCompared with masked PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>
match_d [8]ValueSlaveMask on the PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>
legacy_nfiq [8]SignalSlaveLegacy FIQ interrupt for processor Interface <n>
legacy_nirq [8]SignalSlaveLegacy IRQ interrupt for processor Interface <n>
cfgsdisableSignalSlaveSet preventing write accesses to security-critical configuration registers
reset_inSignalSlaveReset signal
spi [988]SignalSlaveShared peripheral interrupt inputs

Additional protocols

The PL390_GIC component has no additional protocols.

Parameters

Table 5.86 provides a description of the configuration parameters for the PL390_GIC component.

Table 5.86. PL390_GIC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
ARCHITECTURE_VERSIONSet architecture version in periph_id registerInteger0 - 11
AXI_IF Booleantrue/falsetrue
C_ID_WIDTHWidth of the processor interface master idInteger0 - 3232
D_ID_WIDTHWidth of the distributor interface master idInteger0 - 3232
ENABLE_LEGACY_FIQProvide legacy fiq interrupt inputs Booleantrue/falsetrue
ENABLE_LEGACY_FIQProvide legacy irq interrupt inputsBooleantrue/falsetrue
ENABLE_PPI_EDGEppi edge sensitiveBooleantrue/falsefalse
ENABLE_TRUSTZONESupport trust zone Booleantrue/falsetrue
INIT_ENABLE_C0 to INIT_ENABLE_C7init value of ENABLE_C<n>Integer-0xFFFFFFFF
INIT_ENABLE_D0 to INIT_ENABLE_D7init value of ENABLE_D<n>Integer-0xFFFFFFFF
INIT_MATCH_C0 to INIT_MATCH_C7init value of MATCH_C<n>Integer-0xFFFFFFFF
INIT_MATCH_D0 to INIT_MATCH_D7init value of MATCH_D<n>Integer-0xFFFFFFFF
NUM_CPUNumber of processor interfacesInteger1 - 88
NUM_LSPINumber of lockable SPIsInteger0 - 3131
NUM_PPINumber of private peripheral interruptsInteger0 - 1616
NUM_PRIORITY_LEVELSNumber of priority levelsInteger16, 32, 64, 128, 256 256
NUM_SGINumber of software generated interruptsInteger0 - 1616
NUM_SPINumber of shared peripheral interruptsInteger0 - 988988

Registers

Table 5.87 and Table 5.88 provide a description of the configuration registers for the PL390_GIC component. In these tables <n> corresponds to the number of a processor interface. A processor interface consists of a pair of interfaces: pvbus_cpu and pvbus_distributor. The enable_c<n> and match_c<n> signals identify the originator of a transaction on pvbus_cpu. Similarly, enable_d<n> and match_d<n> signals are used to identify the originator of a transaction on pvbus_distributor.

Note

To reduce compile time, the registers are not available by default. To activate them uncomment one of the following statements in PL390_GIC.lisa:

// #define FEW_CADI_REGISTER
// #define ALL_CADI_REGISTER

Table 5.87. PL 390_GIC registers: Distributor Interface

Register nameOffsetAccessDescription
enable0xD0000read/writeICDICR [S]: Interrupt Control Register
enable_ns0xD0001read/writeICDICR [NS]: Interrupt Control Register
ic_type0xD0008 read onlyICDDIIR: Distributor Implementer Identification Register
sgi_security_if<n>0xDn080read/writeICDISR: SGI Interrupt Security Register Interrupt ID 0-15
ppi_security_if<n>0xDn080read/writeICDISR: PPI Interrupt Security Register Interrupt ID 16-31
spi_security_0-310xD0084read/writeICDISR: SPI Interrupt Security Register Interrupt ID 32-63
spi_security_32-630xD0088read/writeICDISR: SPI Interrupt Security Register Interrupt ID 64-95
...   
spi_security_960-9870xD00FCread/writeICDISR: SPI Interrupt Security Register Interrupt ID 992-1019
sgi_enable_set_if<n> 0xDn100read onlyICDISER: SGI Enable Set Register Interrupt ID 0-15
ppi_enable_set_if<n> 0xDn100read onlyICDISER: PPI Enable Set Register Interrupt ID 16-31
spi_enable_set_0-310xD0104read onlyICDISER: SPI Enable Set Register Interrupt ID 32-63
spi_enable_set_32-630xD0108read onlyICDISER: SPI Enable Set Register Interrupt ID 64-95
...   
spi_enable_set_960-9870xD017Cread onlyICDISER: SPI Enable Set Register Interrupt ID 922-1019
sgi_enable_clear_if<n>0xDn180read onlyICDICER: SGI Enable Clear Register Interrupt ID 0-15
ppi_enable_clear_if<n>0xDn182read onlyICDICER: SGI Enable Clear Register Interrupt ID 16-31
spi_enable_clear_0-310xDn182read onlyICDICER: SGI Enable Clear Register Interrupt ID 32-63
spi_enable_clear_32-630xD0188read onlyICDICER: SGI Enable Clear Register Interrupt ID 32-63
...   
spi_enable_clear_960-9870xD01FCread onlyICDICER: SGI Enable Clear Register Interrupt ID 32-63
sgi_pending_set_if<n>0xDn200read onlyICDISPR: SGI Pending Set Register Interrupt ID 0-15
ppi_pending_set_if<n>0xDn202read onlyICDISPR: PPI Pending Set Register Interrupt ID 16-31
spi_pending_set_0-310xD0204read onlyICDISPR: SPI Pending Set Register Interrupt ID 32-63
spi_pending_set_32-630xD0208read onlyICDISPR: SPI Pending Set Register Interrupt ID 64-95
...   
spi_pending_set_960-9870xD027Cread onlyICDISPR: SPI Pending Set Register Interrupt ID 992-1019
sgi_pending_clear_if<n>0xDn280read onlyICDICPR: SGI Pending Clear Register Interrupt ID 0-15
ppi_pending_clear_if<n>0xDn282read onlyICDICPR: SGI Pending Clear Register Interrupt ID 16-31
spi_pending_clear_0-310xDn284read onlyICDICPR: SGI Pending Clear Register Interrupt ID 32-63
spi_pending_clear_32-630xD0288read onlyICDICPR: SGI Pending Clear Register Interrupt ID 64-95
...   
spi_pending_clear_960- 9870xD037Cread onlyICDICPR: SGI Pending Clear Register Interrupt ID 992-1019
priority_sgi_if<n>_0-30xDn400read/writeICDIPR: SGI Priority Level Register Interrupt ID 0-3
...   
priority_sgi_if<n>_12-150xDn40Cread/writeICDIPR: SGI Priority Level Register Interrupt ID 12-15
priority_ppi_if<n>_0-3 0xDn410read/writeICDIPR: PPI Priority Level Register Interrupt ID 16-19
...   
priority_ppi_if<n>_12-150xDn41Cread/writeICDIPR: PPI Priority Level Register Interrupt ID 28-31
priority_spi_0-30xD0420read/writeICDIPR: PPI Priority Level Register Interrupt ID 28-31
...   
priority_spi_984-9870xD07F8 read/writeICDIPR: PPI Priority Level Register Interrupt ID 28-31
target_sgi_i<n>0_0-30xDn800read onlyICDIPTR: SGI Target Register Interrupt ID 0-3
...   
target_sgi_i<n>0_12-150xDn80Cread onlyICDIPTR: SGI Target Register Interrupt ID 12-15
target_ppi_i<n>0_0-30xDn810 read onlyICDIPTR: PPI Target Register Interrupt ID 16-19
...   
target_ppi_i<n>0_12-150xDn81C read onlyICDIPTR: PPI Target Register Interrupt ID 28-31
target_spi_0-30xD0820 read/writeICDIPTR: SPI Target Register Interrupt ID 32-35
...   
target_spi_984-9870xD0BF8 read/writeICDIPTR: SPI Target Register Interrupt ID 32-35
sgi_config_if<n>_0-150xDnC00 read onlyICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15
ppi_config_if<n>_0-150xDnC04 read onlyICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15
spi_config_0-150xD0C08 read/writeICDICR: SPI Interrupt Configuration Register Interrupt ID 32-47
...   
spi_config_976-9870xD0CFC read/writeICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
ppi_if<n>0xDnD00 read onlyICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
spi_0-310xD0D04 read onlyICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
...   
spi_960-9870xD0D7C read onlySPI Status Register Interrupt ID 992-1019
legacy_int<n> 0xDnDD0 read onlyLegacy Interrupt Register
match_d<n>0xDnDE0 read onlyMatch Register
enable_d<n>0xDnDE4 read onlyEnable Register
sgi_control 0xD0F00 read/writeICDSGIR: Software Generated Interrupt Register
periph_id_d_80xD0FC0 read onlyPeripheral Identification Register 8
periph_id_d_4-70xD0FD0 read onlyPeripheral Identification Register [7:4]
periph_id_d_0-30xD0FE0 read onlyPeripheral Identification Register [7:4]
component_id 0xD0FF0 read onlyPrimeCell Identification Register

Debug features

The PL390_GIC component provides some registers for functional verification and integration testing.For more information see the Technical Reference Manual.

Verification and testing

The PL390_GIC has been run against the RTL validation suite and has been successfully used in validation platforms.

Performance

The PL390_GIC component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL390_GIC component has no dependencies on external libraries.

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