A.3.3. Internal peripherals

Some ARM processors implement a set of internal peripheral components that are addressed by a range of programmer-visible physical addresses. The content and behavior of these peripherals are IMPLEMENTATION DEFINED.

In default configuration, the AEM implements the set of peripherals defined in Table A.2. These are similar to the devices described in the Cortex-A9 MPCore Technical Reference Manual.

The physical address of the peripherals is given as a fixed offset from the base address. The base address in the VE platform is 0x2C000000. When using the AEM as a component in other platforms, you can configure the base address with the PERIPHBASE parameter.

Each component can also contain one or more interrupt sources, which are connected to the internal Generic Interrupt Controller (GIC) at the ID numbers specified.

Table A.2. Internal peripherals

PeripheralAddress rangeInterrupt
SCU0x0000 - 0x00FF 
GIC0x0100 - 0x01FF

Legacy IRQ - 31

Legacy FIQ - 28

Global Timer0x0200 - 0x02FF27
Local Timer and Watchdog0x0600 - 0x06FF

Watchdog - 30

Local Timer - 29

Interrupt Distributer0x1000 - 0x1FFF 

use_Cortex-A15_peripherals mode

When the parameter use_Cortex-A15_peripherals is set to true, the AEM implements the set of peripherals defined in Table A.3. These are similar to the devices described in the Cortex-A15 Technical Reference Manual.

Table A.3. Internal peripherals (use_Cortex-A15_peripherals)

PeripheralAddress range
Reserved0x0000 - 0x0FFF
Interrupt Controller Distributer0x1000 - 0x1FFF
Interrupt Controller Physical CPU Interface0x2000 - 0x3FFF
Interrupt Controller Virtual CPU Interface (Hypervisor view for requesting processor)0x4000 - 0x4FFF
Interrupt Controller Virtual CPU Interface (Hypervisor view for all processors)0x5000 - 0x5FFF
Interrupt Controller Virtual CPU Interface (Virtual Machine view)0x6000 - 0x7FFF

The interrupt controller is a Virtualized Generic Interrupt Controller (VGIC).

Note

The generic timer becomes available by CP15 system control operations.

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