5.4.21. PL310_L2CC component

The PL310_L2CC provides a model of an Level 2 Cache Controller (L2CC). The presence of additional on-chip secondary cache can improve performance when significant memory traffic is generated by the processor. A secondary cache assumes the existence of a Level 1, or primary, cache, which is closely coupled or internal to the processor. For more information, see the component documentation. See the ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual. For more information about the accuracy and functionality of Fast Models and cache models, see Chapter 2 Accuracy and Functionality.

The PL310_L2CC component has two modes of operation:

The mode of operation is controlled by a parameter to the component. See Parameters, parameter cache-state_modelled.

Figure 5.42 shows a view of the component in System Canvas.

Figure 5.42. PL310_L2CC in System Canvas

PL310_L2CC in System Canvas

This component is written in LISA+.

The PL310 is only supported when connected to the Cortex-A5 or Cortex-A9 processor. An example system is shown in Figure 5.43.

Figure 5.43. PL310_L2CC in an example system

PL310_L2CC in an example system


Table 5.71 provides a brief description of the PL310_L2CC component ports. For more information, see the component documentation.

Table 5.71. PL310_L2CC ports

NamePort protocolTypeDescription
pvbus_sPVBusSlaveSlave port for connection to PV bus master/decoder
pvbus_mPVBusMasterMaster port for connection to PV bus master/decoder
DECERRINTRSignalMasterDecode error received on master port from L3
ECNTRINTRSignalMasterEvent counter overflow / increment
ERRRDINTRSignalMasterError on L2 data RAM read
ERRRTINTRSignalMasterError on L2 tag RAM read
ERRWDINTRSignalMasterError on L2 data RAM write
ERRWTINTRSignalMasterError on L2 tag RAM write
L2CCINTRSignalMasterCombined interrupt output
PARRDINTRSignalMasterParity error on L2 data RAM read
PARRTINTRSignalMasterParity error on L2 tag RAM read
SLVERRINTRSignalMasterSlave error on master port from L3

Additional protocols

The PL310_L2CC component has no additional protocols.


Table 5.72 lists the parameters in the PL310_L2CC.

Table 5.72. PL310_L2CC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
ASSOCIATIVITYAssociativity for auxiliary control registerInteger0 (8-way), 1 (16-way)0
CACHEIDCache controller cache IDInteger0 - 630
cache-state_modelled[a]Specifies whether real cache state is modeled (vs. register model)Booleantrue/falsefalse
CFGBIGEND Big-endian mode for accessing configuration registers out of resetInteger0,10
LOCKDOWN_BY_LINE[b]Lockdown by lineInteger0,10
LOCKDOWN_BY_MASTER[c]Lockdown by masterInteger0,10
REGFILEBASE Base address for accessing configuration registersInteger0 - 0xfffff0000x1f002000
WAYSIZESize of ways for auxiliary control registerInteger0 - 71

[a] To understand the performance impact of enabling this parameter, see section Performance.

[b] Value is reflected in CacheType register bit 25, but the feature is not switched off when the parameter is 0.

[c] Value is reflected in CacheType register bit 26, but the feature is not switched off when the parameter is 0.


Table 5.73 provides a description of the configuration registers for the PL310_L2CC component.

Table 5.73. PL310_L2CC registers

Register nameOffsetAccessDescription
CacheID0x000read onlyr0 cache ID
CacheType0x004read onlyr0 cache type
Ctrl0x100read/writer1 control
AuxCtrl0x104read/writer1 auxiliary control
TagLatencyCtrl[a]0x108read/writer1 tag RAM latency control
DataLatencyCtrl[a]0x10Cwrite onlyr1 data RAM latency control
EventCounterCtrl[a]0x200read/writer2 event counter control
EventCounter1Cfg[a][a]0x204write onlyr2 event counter 1 configuration
EventCounter0Cfg[a]0x208read/writer2 event counter0 configuration
EventCounter1[a]0x20Cread/writer2 event counter 1 value
EventCounter0[a]0x210read/writer2 event counter 0 value
InterruptMask0x214read/writer2 interrupt mask
MaskedInterruptStatus0x218read onlyr2 masked interrupt status
RawInterruptStatus0x21Cread onlyr2 raw interrupt status
InterruptClear0x220write onlyr2 interrupt clear
CacheSync[a]0x730read/writer7 cache sync
InvalidateByPA0x770read/writer7 invalidate line by PA
InvalidateByWay0x77Cread/writer7 invalidate by way
CleanByPA0x7B0read/writer7 clean line by PA
CleanByIdxWay0x7B8read/writer7 clean line by index or way
CleanByWay0x7BCread/writer7 clean by way
CleanInvalByPA0x7F0read/writer7 clean and invalidate line by PA
CleanInvalByIdxWay0x7F8read/writer7 clean and invalidate line by index or way
CleanInvalByWay0x7FCread/writer7 clean and invalidate by way
DataLockdown00x900read/writer9 data lockdown 0 by way
InstructionLockdown00x904read/writer9 instruction lockdown 0 by way
DataLockdown10x908read/writer9 data lockdown 1 by way
InstructionLockdown10x90Cread/writer9 instruction lockdown 1 by way
DataLockdown20x910read/writer9 data lockdown 2 by way
InstructionLockdown20x914read/writer9 instruction lockdown 2 by way
DataLockdown30x918read/writer9 data lockdown 3 by way
InstructionLockdown30x91Cread/writer9 instruction lockdown 3 by way
DataLockdown40x920read/writer9 data lockdown 4 by way
InstructionLockdown40x924read/writer9 instruction lockdown 4 by way
DataLockdown50x928read/writer9 data lockdown 5 by way
InstructionLockdown50x92Cread/writer9 instruction lockdown 5 by way
DataLockdown60x930read/writer9 data lockdown 6 by way
InstructionLockdown60x934read/writer9 instruction lockdown 6 by way
DataLockdown70x938read/writer9 data lockdown 7 by way
InstructionLockdown70x93Cread/writer9 instruction lockdown 7 by way
LockdownByLineEnable0x950read/writer9 lockdown by line enable
UnlockAll0x954read/writer9 unlock all lines by way
AFilterStart[a]0xC00read/writer12 address filtering start
AFilterEnd[a]0xC04read/writer12 address filtering end
DebugControl[a]0xF40read/writer15 debug control register

[a] Operation of this register is not functionally modeled.

Debug features

The PL310_L2CC component exports the PL310 registers by CADI.

Verification and testing

The PL310_L2CC has been run against the RTL validation suite and passes for supported features. It has also been tested with operating system booting in both normal and exclusive modes, and has successfully used in validation platforms.


The performance of the PL310_L2CC component depends on the configuration of the associated L1 caches and the mode it is in.

  • register mode: The PL310_L2CC model does not significantly affect performance.

  • functional mode with functional-mode L1: the addition of a functional L2 cache has minimal further impact on performance when running applications that are cache-bound.

  • functional mode with a register-mode L1: the PL310_L2CC has a significant impact on system performance in this case.

Library dependencies

The PL310_L2CC component has no dependencies on external libraries.


The PL310 implements the programmer visible functionality of the PL310, and excludes some non-programmer visible features.

Implemented hardware features

The following features of the PL310 hardware are implemented in the PL310 model:

  • Physically addressed and physically tagged.

  • Lockdown format C supported, for data and instructions. Lockdown format C is also known as way locking.

  • Lockdown by line supported.

  • Lockdown by master id supported.

  • Direct mapped to 16-way associativity, depending on the configuration and the use of lockdown registers. The associativity is configurable as 8 or 16.

  • L2 cache available size can be 16KB to 8MB, depending on configuration and the use of the lockdown registers.

  • Fixed line length of 32 bytes (eight words or 256 bits).

  • Supports all of the AXI cache modes:

    • write-through and write-back.

    • read allocate, write allocate, read and write allocate.

  • Force write allocate option to always have cacheable writes allocated to L2 cache, for processors not supporting this mode.

  • Normal memory non-cacheable shared reads are treated as cacheable non-allocatable. Normal memory non-cacheable shared writes are treated as cacheable write-through no write-allocate. There is an option, Shared Override, to override this behavior.

  • TrustZone support, with the following features:

    • Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as an address bit.

    • NS bit in Tag RAM used to determine security level of evictions to L3.

    • Restrictions for NS accesses for control, configuration, and maintenance registers to restrict access to secure data.

  • Pseudo-Random victim selection policy. You can make this deterministic with use of lockdown registers.

  • Software option to enable exclusive cache configuration.

  • Configuration registers accessible using address decoding in the component.

  • Interrupt triggering in case of an error response when accessing L3.

  • Maintenance operations.

  • Prefetching capability.

Hardware features not implemented

The following features of the PL310 hardware are not implemented in the PL310 model, most of them are not relevant from a PV modeling point of view:

  • There is no interface to the data and tag RAM as they are embedded to the model.

  • Critical word first linefill not supported, as this is not relevant for PV modeling.

  • Buffers are not modeled.

  • Outstanding accesses on slave and master ports cannot occur by design in a PV model as all transactions are atomic.

  • Option to select one or two master ports and option to select one or two slave ports is not supported. Only one master port and one slave port is supported.

  • Clock management and power modes are not supported, as they is not relevant for PV modeling.

  • Wait, latency, clock enable, parity, and error support for data and tag RAMs not included, as this is not relevant for PV modeling, and the data and tag RAMs embedded in the model cannot generate error responses.

  • MBIST support is not included.

  • Debug mode and debug registers are not supported.

  • Test mode and scan chains are not supported.

  • L2 cache event monitoring is not supported.

  • Address filtering in the master ports is not supported.

  • Performance counters are not supported.

  • Specific Cortex-A9 related optimizations are not supported: Prefetch hints, Full line of zero and Early write response.

  • Hazard detection is not required because of the atomic nature of the accesses at PV modeling and the fact that buffers are not modeled, thus hazards cannot occur.

Registers belonging to features not implemented are accessible but do not have a functionality.

Features additional to the Hardware
  • Data RAM and Tag RAM are embedded to the model.

Features different to the Hardware
  • Error handling. DECERR from the master port is mapped to SLVERR. Internal errors in cache RAM (like parity errors) cannot happen in the model.

  • Background cache operations do not occur in the background. They occur atomically.

  • The LOCKDOWN_BY_LINE and LOCKDOWN_BY_MASTER parameter values are reflected in the CacheType register, but the feature is not switched off when the parameter is 0.

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