5.4.16. PL110_CLCD component

The PL110_CLCD component provides a programmer’s view model of the PL110 Color LCD (CLCD) controller PrimeCell. The model can be connected through a framebuffer port to, for instance, a visualization component, so that LCD output can be viewed.

The implementation is intended to provide a register model of the LCD controller and both timing and bus utilization models are made deliberately inaccurate to favor efficiency of implementation and model speed.

Figure 5.37 shows a view of the component in System Canvas.

Figure 5.37. PL110_CLCD in System Canvas

PL110_CLCD in System Canvas

This component is written in LISA+.


Table 5.58 provides a brief description of the ports. See also the ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual.

Table 5.58. PL110_CLCD ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
intrSignalMasterInterrupt signaling for flyback events.
clk_inClockSignalSlaveMaster clock input, typically 24MHz, to drive pixel clock timing.
displayLCDMasterConnection to visualization component. See Visualisation Library.
controlValueSlaveAuxiliary control register 1.
pvbus_mPVBusMasterDMA port for video data.

Additional protocols

The PL110_CLCD component has no additional protocols.


Table 5.59 provides a description of the configuration parameters for the PL110_CLCD component.

Table 5.59. PL110_CLCD configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
pixel_double_limitSets a threshold in horizontal pixels, below which pixels sent to the framebuffer are doubled in size horizontally and vertically.Integer-300


Table 5.60 provides a description of the configuration registers for the PL110_CLCD component.

Table 5.60. PL110_CLCD registers

Register nameOffsetAccessDescription
LCDTiming00x000read/writeHorizontal timing
LCDTiming10x004read/writeVertical timing
LCDTiming20x008read/writeClock and polarity control
LCDTiming30x00Cread/writeLine end control
LCDUPBASE 0x010read/writeUpper panel frame base address
LCDLPBASE0x014read/writeLower panel frame base address
LCDIMSC0x018read/writeInterrupt mask
LCDRIS0x020read onlyRaw interrupt status
LCDMIS0x024read onlyMasked interrupt status
LCDICR0x028write onlyInterrupt clear
LCDIPCURR0x02Cread onlyUpper panel current address
LCDLPCURR0x030read onlyLower panel current address
LCDPalette0x200 - 0x400read/writePalette registers
LCDPeriphID00xfe0readPeripheral ID register
LCDPeriphID10xfe4readPeripheral ID register
LCDPeriphID20xfe8readPeripheral ID register
LCDPeriphID30xfecreadPeripheral ID register
LCDPCellID00xff0readPrimeCell ID register
LCDPCellID10xff4readPrimeCell ID register
LCDPCellID20xff8readPrimeCell ID register
LCDPCellID30xffcreadPrimeCell ID register

Debug features

The PL110_CLCD component has no debug features.

Verification and testing

The PL110_CLCD component has been tested as part of the VE example system using VE test suites and by booting operating systems.


The PL110_CLCD component might affect the performance of a PV system. The implementation is optimized for situations where the majority of the framebuffer does not change. For instance, displaying full screen video results in significantly reduced performance. Rendering pixel data into an appropriate form for the framebuffer port (rasterization) can also take a significant amount of simulation time. If the pixel data are coming from a PVBusSlave region that has been configured as memory-like, rasterization only occurs in regions where memory contents are modified.

Library dependencies

The PL110_CLCD component has no dependencies on external libraries.

Copyright © 2008-2013 ARM. All rights reserved.ARM DUI 0423O