5.4.23. PL340_DMC component

The PL340_DMC component is a programmer’s view model of the ARM PL340 Dynamic Memory Controller (DMC). It provides an interface for up to four DRAM chips. The implementation also provides an apb_interface to configure the controller behavior. Further information is available in the component documentation. See the ARM PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual.

Figure 5.45 shows a view of the component in System Canvas.

Figure 5.45. PL340_DMC in System Canvas

PL340_DMC in System Canvas

This component is written in LISA+.


Table 5.77 provides a brief description of the ports for the PL340_DMC component. For more information, see the component documentation. See the ARM PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual.

Table 5.77. PL340_DMC ports

NamePort protocolTypeDescription
axi_chip_if_in[4]PVBusSlaveSlave bus for connecting to bus decoder
apb_interfacePVBusSlaveSlave bus interface for register access
axi_chip_if_out[4]PVBusMasterMaster to connect to DRAM

Additional protocols

The PL340_DMC component has no additional protocols.


Table 5.78 provides a description of the configuration parameters for the PL340_DMC component.

Table 5.78. PL340_DMC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
MEMORY_WIDTHIndicates the width, in bits, of connected memoryInteger16, 32, 6432
IF_CHIP_0 to IF_CHIP_3Indicates whether memory is connected Integer-1, 0[a]-1

[a] The permitted values have the following meanings:


nothing connected to the interface


DRAM connected.


Table 5.79 provides a description of the configuration registers for the PL340_DMC component. These are accessible through the APB interface.

Table 5.79. PL340_DMC registers

Register nameOffsetAccessDescription
memc_status0x000read onlyMemory controller status register
memc_cmd0x004write onlyUsed to modify the state machine of the controller
direct_cmd0x008write onlyUsed to set the memory controller configurations
memory_cfg0x00Cread/writeSet/read the configuration of the controller
refresh_prd0x010read/writeRefresh period register
cas_latency0x014read/writeCAS latency register
t_dqss0x018read/writet_dqss register
t_mrd0x01Cread/writet_mrd register
t_ras0x020read/writet_ras register
t_rc0x024read/writet_rc register
t_rcd0x028read/writet_rcd register
t_rfc0x02Cread/writet_rfc register
t_rp0x030read/writet_rp register
t_rrd0x034read/writet_rrd register
t_wr0x038read/writet_wr register
t_wtr0x03Cread/writet_wtr register
t_xp0x040read/writet_xp register
t_xsr0x044read/writet_xsr register
t_esr0x048read/writet_esr register
id_00_cfg0x100read/writeSets the QOS
id_01_cfg0x104read/writeSets the QOS
id_02_cfg0x108read/writeSets the QOS
id_03_cfg0x10Cread/writeSets the QOS
id_04_cfg0x110read/writeSets the QOS
id_05_cfg0x114read/writeSets the QOS
id_06_cfg0x118read/writeSets the QOS
id_07_cfg0x11Cread/writeSets the QOS
id_08_cfg0x120read/writeSets the QOS
id_09_cfg0x124read/writeSets the QOS
id_10_cfg0x128read/writeSets the QOS
id_11_cfg0x12Cread/writeSets the QOS
id_12_cfg0x130read/writeSets the QOS
id_13_cfg0x134read/writeSets the QOS
id_14_cfg0x138read/writeSets the QOS
id_15_cfg0x13Cread/writeSets the QOS
chip_0_cfg0x200read/writeSet up the external memory device configuration
chip_1_cfg0x204read/writeSet up the external memory device configuration
chip_2_cfg0x208read/writeSet up the external memory device configuration
chip_3_cfg0x20Cread/writeSet up the external memory device configuration
user_status0x300read onlyUser status register
user_config0x304write onlyUser configuration register
periph_id_00xFE0read onlyPeripheral ID register 0[a]
periph_id_10xFE4read onlyPeripheral ID register 1[a]
periph_id_20xFE8read onlyPeripheral ID register 2[a]
periph_id_30xFECread onlyPeripheral ID register 3[a]
pcell_id_00xFF0read onlyPrimeCell ID register 0[a]
pcell_id_10xFF4read onlyPrimeCell ID register 1[a]
pcell_id_20xFF8read onlyPrimeCell ID register 2[a]
pcell_id_30xFFCread onlyPrimeCell ID register 3[a]

[a] This register has no CADI interface.

Debug features

The PL340_DMC component has no debug features.

Verification and testing

The PL340_DMC functions of the component have been tested individually using a tailored test suite.


The PL340_DMC component has negligible impact on performance.

Library dependencies

The PL340_DMC component has no dependencies on external libraries.

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