A.3.2. TLB lockdown

The ARM architecture defines the concept of TLB lockdown but does not specify the register format used in its implementation. Code that runs portably across ARMv7-A implementations cannot use TLB lockdown except by selecting processor-specific code segments.

The model supports TLB lockdown using the register scheme of the Cortex-A8, only if the size of the TLB is compatible with that format, that is, the TLB contains 32 entries or fewer. TLB lockdown is not available in cases where aggressive TLB pre-fetch is enabled.

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