A.1.1. Aggressively pre-fetching TLB

Rating: 2.

The architecture describes that a processor might at any time request the pagetable entry or entries corresponding to any virtual address. When the Boolean parameter vmsa.tlb_prefetch is set as true, the AEM actively monitors the memory for all pagetables, and immediately updates the Translation Lookaside Buffer (TLB) accounting for any changes.

Also, in this mode the TLB maintains state for old and new entries, and raises the message E_StaleTLB if there is any possible ambiguity as to which entry could have been used in a subsequent transaction.

Note

The aggressively pre-fetching TLB does not currently support the IMPLEMENTATION DEFINED TLB lockdown feature described in TLB lockdown. Lockdown registers are non-operational when the pre-fetching TLB option is in use.

Note

The aggressively pre-fetching TLB does not currently support the Large Physical Address or Virtualization features. TLB pre-fetching does not occur when either lpae or virtualization is implemented in the processor.

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