3.3.1. MasterClock component

The MasterClock component provides a single ClockSignal output that can be used to drive the ClockSignal input of ClockDividers, ClockTimers and other clocking components. The rate of the MasterClock is not defined because all clocking is relative, but can be considered to be 1Hz.

A system might contain more than one MasterClock, all of which generate the same ClockSignal rate.

Figure 3.1 shows a view of the component in System Canvas.

Figure 3.1. MasterClock in System Canvas

MasterClock in System Canvas

This component is written in C++.


Table 3.1 provides a brief description of the ports. For more information, see the component documentation.

Table 3.1. MasterClock ports

NamePort protocolTypeDescription
clk_outClockSignalmastermaster clock rate

Additional protocols

The MasterClock component has no additional protocols.


The MasterClock component has no parameters.


The MasterClock component has no registers.

Debug features

The MasterClock component has no debug features.

Verification and testing

The MasterClock component has been tested as part of the VE example system using VE test suites and by booting operating systems.


The MasterClock component has no effect on the performance of a PV system.

Library dependencies

The MasterClock component has no dependencies on external libraries.

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