The MasterClock component provides a single ClockSignal output that can be used to drive the ClockSignal input of ClockDividers, ClockTimers and other clocking components. The rate of the MasterClock is not defined because all clocking is relative, but can be considered to be 1Hz.
A system might contain more than one MasterClock, all of which generate the same ClockSignal rate.
Figure 3.1 shows a view of the component in System Canvas.
This component is written in C++.
Table 3.1 provides a brief description of the ports. For more information, see the component documentation.
Table 3.1. MasterClock ports
| Name | Port protocol | Type | Description |
|---|---|---|---|
| clk_out | ClockSignal | master | master clock rate |
The MasterClock component has been tested as part of the VE example system using VE test suites and by booting operating systems.
PDF version