5.4.32. RemapDecoder

The RemapDecoder component provides the low memory flash/RAM remap behavior of the example systems.

Figure 5.54 shows a view of the component in System Canvas.

Figure 5.54. RemapDecoder in System Canvas

RemapDecoder in System Canvas

This model is written in LISA+.

Ports

Table 5.101 provides a brief description of the ports of the RemapDecoder component. For more information, see the VE hardware documentation.

Table 5.101. RemapDecoder ports

NamePort protocolTypeDescription
inputPVBusSlaveFor connection to PV bus master/decoder
output_remap_setPVBusMasterFor connection to a component addressable with remap set
output_remap_clearPVBusMasterFor connection to a component addressable with remap clear
remapStateSignalSlaveInput permitting control of remap state
controlTZSwitchControl Internal port. Not for use.

Additional protocols

The RemapDecoder component has no additional protocols.

Parameters

The RemapDecoder component has no parameters.

Registers

The RemapDecoder component has no registers

Debug features

The RemapDecoder component has no debug features.

Verification and testing

The RemapDecoder component has been tested as part of the VE example system using VE test suites and by booting operating systems.

Performance

The RemapDecoder component is not expected to significantly affect the performance of a PV system.

Library dependencies

The RemapDecoder component has no dependencies on external libraries.

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