5.4.49. GIC400 component

The GIC400 component represents the GIC-400 Generic Interrupt Controller (GIC), and includes a Virtualized Generic Interrupt Controller (VGIC). It is a wrapper that permits easier configuration of the v7_VGIC component that supports parameterized configuration. See Figure 5.71:

Figure 5.71. GIC400 in System Canvas

GIC400 in System Canvas

This component is written in LISA+.

The GIC-400 has several memory-mapped interfaces at the same address that are banked by the processor that is communicating with it. Consequently, the GIC-400 must be able to distinguish from which processor a transaction has originated. In the hardware, the GIC-400 is supplied this information in the AUSER fields on AXI. In Fast Models, there is no exact equivalent to this field. However, each transaction has a master_id that the model can choose to use to identify the originating processor.

ARM clusters assign the master_id as follows:

where CLUSTERID is the 4 bit field that is set either by a parameter on the processor or by driving a value on the clusterid port. CPUID is the processor number within the cluster. CLUSTERID appears in the CP15 register space as part of the MPIDR register.

The ARM architecture suggests that each cluster in the system is given a different CLUSTERID, and this is essential for the VGIC to identify the processor. The parameters in the GIC-400 component permit it to construct the map of master_id to interface number.

For each processor interface that the GIC-400 supports, there are the following parameters:

where N is the interface number (0-7). The cluster_id and core_id tell the GIC-400 to map that cluster or processor combination to interface N.

In using inout_port_number_to_use, the GIC-400 has a number of input and output ports that are intended to be paired with a particular processor interface. For example:

To easily support clusters that can have variable numbers of processors, the interfaceN.inout_port_number_to_use parameter tells the GIC-400 that if it wants to send or receive a signal to the processor attached to interface N, then it should use the following pins:

Note

legacyirq and legacyfiq are not signals from the processor but are signals into the GIC-400 from the legacy interrupt system. They are wired to PPIs and can also bypass the GIC-400 if control registers of the GIC-400 are set up in particular ways. See the ARM Generic Interrupt Controller Architecture version 2.0 Architecture Specification for more information.

Note

The fabric between the ARM clusters and the GIC might remap the master_id of a transaction, and if so then the GIC might lose the ability to identify the originating processor. The fabrics that ARM ships in Fast Models perform no such transformation.

The comparison that the GIC-400 performs on the master_id is only on the bottom 6 bits of the master_id, and the rest are ignored. If you are writing your own fabric and do not properly propagate the master_id or transform it, the GIC-400 might not be able to identify the processor correctly. The source code for the GIC_400 component can be examined to see how it might be adapted for it to understand different master_id schemes.

Ports

Table 5.137 provides a brief description of the GIC400 component ports. For more information, see the hardware documentation.

Table 5.137. GIC400 ports

NamePort ProtocolTypeDescription
cfgsdisableSignalslaveDisable write access to some GIC registers.
cnthpirqSignalslaveHypervisor physical timer event.
cntpnsirqSignalslaveNon-secure physical timer event.
cntpsirqSignalslaveSecure physical timer event.
cntvirqSignalslaveVirtual timer event.
fiqcpuSignalmasterFIQ signal to the corresponding processor.
irqcpuSignalmasterIRQ signal to the corresponding processor.
irqsSignalslaveInterrupt request input lines for the GIC.
legacyfiqSignalslaveSignal into the GIC-400 from the legacy interrupt system.
legacyirqSignalslaveSignal into the GIC-400 from the legacy interrupt system.
pvbus_sPVBusslaveHandles incoming transactions fromPVBus masters.
reset_signalSignalslaveReset signal input.
vfiqcpuSignalmasterVirtual FIQ signal to the processor.
virqcpuSignalmasterVirtual IRQ signal to the processor.

Additional protocols

The GIC400 component has no additional protocols.

Parameters

Table 5.138 provides a description of the configuration parameters for the GIC400 component.

Table 5.138. GIC400 configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
NUM_CPUSNumber of interfaces to support.Integer1-81
NUM_SPISNumber of shared peripheral interrupt pins.Integer0-480224
interface0.cluster_idThe CLUSTERID of the interface you want to appear as interface0 in the VGIC.Integer0-150
interface0.core_idThe processor id of interface0 in the cluster.Integer0-150
interface0.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-70
interface1.cluster_idThe CLUSTERID of the processor you want to appear as interface1 in the VGIC.Integer0-150
interface1.core_idThe processor id of interface1 in the cluster.Integer0-150
interface1.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-71
interface2.cluster_idThe CLUSTERID of the interface you want to appear as core0 in the VGIC.Integer0-150
interface2.core_idThe processor id of core0 in the cluster.Integer0-150
interface2.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-72
interface3.cluster_idThe CLUSTERID of the interface you want to appear as interface3 in the VGIC.Integer0-150
interface3.core_idThe processor id of interface3 in the cluster.Integer0-150
interface3.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-73
interface4.cluster_idThe CLUSTERID of the interface you want to appear as interface4 in the VGIC.Integer0-150
interface4.core_idThe processor id of interface4 in the cluster.Integer0-150
interface4.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-74
interface5.cluster_idThe CLUSTERID of the interface you want to appear as interface5 in the VGIC.Integer0-150
interface5.core_idThe processor id of interface5 in the cluster.Integer0-150
interface5.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-75
interface6.cluster_idThe CLUSTERID of the interface you want to appear as interface6 in the VGIC.Integer0-150
interface6.core_idThe processor id of interface6 in the cluster.Integer0-150
interface6.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-76
interface7.cluster_idThe CLUSTERID of the interface you want to appear as interface7 in the VGIC.Integer0-150
interface7.core_idThe processor id of interface7 in the cluster.Integer0-150
interface7.inout_port_number_to_useWhich ppiN port is used for this interface.Integer0-77

Registers

The GIC400 component has no registers.

Debug Features

The GIC400 component has no debug features.

Verification and testing

The GIC400 component has been tested as part of a system with network functionalities.

Performance

The GIC400 component is not expected to significantly affect the performance of a PV system.

Library dependencies

The GIC400 component has no dependencies on external libraries.

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