5.2.1. About the PVBus components

The PVBus components and protocols provide mechanisms for implementing functionally-accurate communication between bus masters and slaves. There is no modeling of handshaking or cycle counts. By removing this level of detail, and by using efficient internal communication mechanisms, PVBus components can provide very fast modeling of bus accesses.

PVBus components are not software implementations of specific hardware, but are instead abstract components required for the software model environment.

The PVBus API is accessed through a number of components, which abstract the internal details. These components must be used correctly to achieve high simulation speeds.

PVBus system components

A bus system consists of a number of bus masters, some infrastructure and a number of bus slaves. Each bus master must contain a PVBusMaster subcomponent, and each bus slave must contain a PVBusSlave subcomponent. These subcomponents provide PVBus master and slave ports. Each PVBus master port can only be connected to one slave, but any number of other masters can be connected to the same slave. PVBusDecoder, PVBusMaster and PVBusSlave components communicate using the PVBus protocol.

PVBusDecoder components can be added to the bus system. Each of these permits its masters to be connected to multiple slaves, each associated with a different bus address range.

PVBusSlave subcomponents provide built-in support for declaring memory-like, device-like, abort or ignore address ranges. PVBus has support for dealing efficiently with memory-like devices such as RAM, ROM and Flash.

Figure 5.1 demonstrates a sample bus topology:

Figure 5.1. Sample bus topology

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All communication over the PVBus is performed using transactions that are generated by PVBusMaster subcomponents and fulfilled by PVBusSlave components. Transactions can be routed to the slave device through its PVBusSlave subcomponent. When configured, the PVBusSlave can handle memory-like transactions efficiently without having to route these transactions to the slave device. All transactions are atomic and untimed, in keeping with the programmer’s view abstraction.

PVBus examples

This document contains some examples of PVBus components in use. Additional examples can be found in Fast Models. Paths to these examples are provided in Table 5.1. For paths on Linux, substitute $PVLIB_HOME for the Microsoft Windows environment variable %PVLIB_HOME%.

Table 5.1. PVBus examples

PathDescription

%PVLIB_HOME%\LISA\CounterModule.lisa

A full implementation of a bus slave device (CounterTimer module).

%PVLIB_HOME%\examples\FVP_EB\LISA\FVP_EB_ARM1176.lisa

Example of moderately complex bus topology, using the PVBusDecoder component.

%PVLIB_HOME%\examples\Common\LISA\RemapDecoder.lisa

An example that dynamically modifies routing of requests based on a remap signal, using the TZSwitch component.


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