4.19.4. TLB

Translation Lookaside Buffers (TLBs) are implemented in the PV models and most aspects of TLB behavior are fully modeled. Memory attribute settings in TLB entries are currently ignored by PV models of processors because they relate to cache and write buffer behavior.

Note

If the device-accurate-tlb parameter is set to false, a different number of TLBs is used for the simulation if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Set device-accurate-tlb parameter to true if device accuracy is required.

TLB registers which have implementations that read as 0 and ignore writes are:

Additional registers affected on the ARMCortexA9 model are:

Additional registers affected on the ARMCortexA8 model are:

Additional registers affected on the ARM1176CT model are:

Additional registers affected on the ARM1136CT model are:

In addition peripheral accesses are not distinguished from data accesses so configuration of the peripheral port memory remap register is ignored.

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