4.19.1. Caches

ARMv7 processor PV models, such as the Cortex-A9, Cortex-A8, and Cortex-R4, have PV-accurate cache implementation. This means that the cache implementation is sufficient to provide a functionally-accurate model. See the relevant processor component descriptions to find out what specific features are implemented.

All other PV models do not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations are modeled to permit cache aware software to work, but in most cases they perform no operation other than to check register access permissions.

The registers affected on all code translation processor models are:

Additional registers affected on the ARMCortexA8CT model are:

Additional registers affected on the ARMCortexR4CT model are:

One additional register is affected on the ARM1176CT model:

Additional registers affected on the ARM1136CT model are:

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