2.2.1. Configuring functional caches

Functional caches are, by default, disabled. Configuration parameters are described in Table 2.1.

Table 2.1. Parameters to control functional cache behavior

ComponentParameterDescriptionTypeAllowed valueDefault value
Cortex-A15[a]l1_dcache-state_modelledSet whether L1 D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A15[a]l1_icache-state_modelledSet whether L1 I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A15[a]l2_cache-state_modelledEnable unified Level 2 cache state model.Booleantrue/falsefalse
Cortex-A9dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A9icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A8[a]l1_dcache-state_modelledSet whether L1 D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A8[a]l1_icache-state_modelledSet whether L1 I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A8[a]l2_cache-state_modelledEnable unified Level 2 cache state model.Booleantrue/falsefalse
Cortex-A7l1_dcache-state_modelledSet whether L1 D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A7l1_icache-state_modelledSet whether L1 I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A7l2_cache-state_modelledEnable unified Level 2 cache state model.Booleantrue/falsefalse
Cortex-A5dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-A5icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-R7dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-R7icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue/falsefalse
Cortex-R4dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue/falsefalse
Cortex-R4icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue/falsefalse
PL310 L2CCcache-state_modelledEnable unified Level 2 cache state model.Booleantrue/falsefalse

[a] Correct modeling of hardware-maintained coherency requires that l2_cache-state_modelled is enabled if any of the per processor l1_dcache-state_modelled parameters are enabled.


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