2.3.4. Out-of-order execution and write-buffers

The current CT implementation always executes instructions sequentially in program order. One instruction is completely retired before the next starts to execute. In a real processor, multiple memory accesses can be outstanding at once, and can complete in a different order from their program order. Writes can also be delayed in a write-buffer.

The programmer visible effects of these behaviors is defined in the architecture as the Weakly Ordered memory model, which the programmer must be aware of when writing lock-free multiprocessor code.

Within Fast Models, all memory accesses can be observed to happen in program order, effectively as if all memory is Strongly Ordered.

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