4.2.1. Ports

Table 4.1 provides a brief description of the ports in the ARMCortexA15xnCT component. For more information, see the processor technical reference manual.

Table 4.1. ARMCortexA15xnCT ports

NamePort ProtocolTypeDescription
CNTHPIRQ[0-3]SignalmasterHypervisor physical timer event
CNTPNSIRQ[0-3]SignalmasterNon-secure physical timer event
CNTPSIRQ[0-3]SignalmasterSecure physical timer event
CNTVIRQ[0-3]SignalmasterVirtual timer event
acp_sPVBusslaveAdvanced eXtensible Interface (AXI™) ACP slave port
cfgend[0-3]SignalslaveInitialize to BE8 endianness after a reset.
cfgsdisableSignalslaveDisable write access to some Generic Interrupt Controller (GIC) registers.
clk_inClockSignalslaveMain processor clock input.
clusteridValueslaveSets the value in the CLUSTERID field (bits[11:8]) of the MPIDR.
cntvaluebPrivateslaveSynchronous counter value. This must be connected to the MemoryMappedCounterModule component.
cpuporeset[0-3]SignalslavePower on reset. Initializes all the processor logic, including the NEON and VFP logic, Debug, PTM, breakpoint and watchpoint logic in the processor CLK domain.
cp15sdisable[0-3]SignalslaveDisable write access to some secure cp15 registers.
eventSignalpeerEvent input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
fiq[0-3]SignalslaveProcessor FIQ signal input.
irq[0-3]SignalslaveProcessor IRQ signal input.
irqs[0-223]SignalslaveShared peripheral interrupts.
l2resetSignalslaveReset shared L2 memory system, interrupt controller and timer logic.
periphbaseValueslaveBase of private peripheral region.
pmuirq[0-3]SignalmasterPerformance Monitoring Unit (PMU) interrupt signal.
presetdbgSignalslaveInitializes the shared debug APB, Cross Trigger Interface (CTI), andCross Trigger Matrix (CTM) logic.
pvbus_m0PVBusmasterAXI bus master channel.
reset[0-3]SignalslaveIndividual processor reset signal.
standbywfe[0-3]SignalmasterIndicates if a processor is in Wait For Event (WFE) state.
standbywfi[0-3]SignalmasterIndicates if a processor is in Wait For Interrupt (WFI) state.
teinit[0-3]SignalslaveInitialize to take exceptions in T32 state after a reset.
ticks[0-3]InstructionCountmasterProcessor instruction count for visualization.
vfiq[0-3]SignalslaveProcessor virtual FIQ signal input.
vinithi[0-3]SignalslaveInitialize with high vectors enabled after a reset.
virq[0-3]SignalslaveProcessor virtual IRQ signal input.

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