CNTHPIRQ[0-3] | Signal | master | Hypervisor physical timer event |
CNTPNSIRQ[0-3] | Signal | master | Non-secure physical timer event |
CNTPSIRQ[0-3] | Signal | master | Secure physical timer event |
CNTVIRQ[0-3] | Signal | master | Virtual timer event |
acp_s | PVBus | slave | Advanced eXtensible Interface (AXI™) ACP slave port |
cfgend[0-3] | Signal | slave | Initialize to BE8 endianness after a reset. |
cfgsdisable | Signal | slave | Disable write access to some Generic Interrupt
Controller (GIC) registers. |
clk_in | ClockSignal | slave | Main processor clock input. |
clusterid | Value | slave | Sets the value in the CLUSTERID field (bits[11:8])
of the MPIDR. |
cntvalueb | Private | slave | Synchronous counter value. This must be connected
to the MemoryMappedCounterModule component. |
cpuporeset[0-3] | Signal | slave | Power on reset. Initializes all the processor
logic, including the NEON and VFP logic, Debug, PTM, breakpoint and
watchpoint logic in the processor CLK domain. |
cp15sdisable[0-3] | Signal | slave | Disable write access to some secure cp15 registers. |
event | Signal | peer | Event input and output for wakeup from WFE.
This port amalgamates the EVENTI and EVENT0 signals that are present
on hardware. |
fiq[0-3] | Signal | slave | Processor FIQ signal input. |
irq[0-3] | Signal | slave | Processor IRQ signal input. |
irqs[0-223] | Signal | slave | Shared peripheral interrupts. |
l2reset | Signal | slave | Reset shared L2 memory system, interrupt controller
and timer logic. |
periphbase | Value | slave | Base of private peripheral region. |
pmuirq[0-3] | Signal | master | Performance Monitoring Unit (PMU) interrupt
signal. |
presetdbg | Signal | slave | Initializes the shared debug APB, Cross Trigger
Interface (CTI), andCross Trigger Matrix (CTM) logic. |
pvbus_m0 | PVBus | master | AXI bus master channel. |
reset[0-3] | Signal | slave | Individual processor reset signal. |
standbywfe[0-3] | Signal | master | Indicates if a processor is in Wait
For Event (WFE) state. |
standbywfi[0-3] | Signal | master | Indicates if a processor is in Wait
For Interrupt (WFI) state. |
teinit[0-3] | Signal | slave | Initialize to take exceptions in T32 state after
a reset. |
ticks[0-3] | InstructionCount | master | Processor instruction count for visualization. |
vfiq[0-3] | Signal | slave | Processor virtual FIQ signal input. |
vinithi[0-3] | Signal | slave | Initialize with high vectors enabled after a
reset. |
virq[0-3] | Signal | slave | Processor virtual IRQ signal input. |
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