4.2.6. Debug Features

The ARMCortexA15xnCT component exports a CADI debug interface.


All processor, VFP, CP14 and CP15 registers, apart from performance counter registers, are visible in the debugger. All CP14 debug registers are implemented. See the processor technical reference manual for a detailed description of available registers.


There is direct support for:

  • single address unconditional instruction breakpoints

  • unconditional instruction address range breakpoints

  • single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The current models support processor exception breakpoints by the use of pseudoregisters available in the debugger register window. When debugger support is added to directly support processor exceptions, these pseudoregisters are removed.

Setting an exception register to a nonzero value cause execution to stop on entry to the associated exception vector.


The ARMCortexA15xnCT component presents three 4GB views of virtual address space, that is, one in hypervisor, one in secure mode and one in non-secure mode.

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