4.3.1. Ports

Table 4.4 provides a brief description of the ports in the ARMCortexA9MPxnCT component. For more information, see the processor technical reference manual.

Table 4.4. ARMCortexA9MPxnCT ports

NamePort protocolTypeDescription
acp_sPVBusslaveSlave channel
cfgend[0-3]SignalslaveInitialize to BE8 endianness after a reset.
cfgnmfi[0-3]SignalslaveEnable nonmaskable FIQ interrupts after a reset.
cfgsdisableSignalslaveDisable write access to some GIC registers.
clk_inClockSignalslaveMain processor clock input.
clusteridValueslaveValue read in MPIDR register.
cp15sdisable[0-3]SignalslaveDisable write access to some cp15 registers.
eventSignalpeerEvent input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
filterenSignalslaveEnable filtering of address ranges between master bus ports.
filterendValueslaveEnd of region mapped to pvbus_m1.
filterstartValueslaveStart of region mapped to pvbus_m1.
fiq[0-3]SignalslaveProcessor FIQ signal input.
irq[0-3]SignalslaveProcessor IRQ signal input.
ints[0-223]SignalslaveShared peripheral interrupts.
periphbaseValueslaveBase of private peripheral region.
periphclk_inClockSignalslaveTimer/watchdog clock rate.
periphresetSignalslaveTimer and GIC reset signal.
pmuirq[0-3]SignalmasterPerformance Monitoring Unit (PMU) interrupt signal.
pvbus_m0PVBusmasterAXI master 0 bus master channel.
pvbus_m1PVBusmasterAXI master 1 bus master channel.
pwrctli[0-3]ValueslaveReset value for SCU processor status register.
pwrctlo[0-3]ValuemasterSCU processor status register bits.
reset[0-3]SignalslaveIndividual processor reset signal.
scuresetSignalslaveSCU reset signal.
smpnamp[0-3]SignalmasterIndicates which processors are in SMP mode.
standbywfe[0-3]SignalmasterIndicates if a processor is in WFE state.
standbywfi[0-3]SignalmasterIndicates if a processor is in WFI state.
teinit[0-3]SignalslaveInitialize to take exceptions in T32 state after a reset.
ticks[0-3]InstructionCountmasterProcessor instruction count for visualization.
vinithi[0-3]SignalslaveInitialize with high vectors enabled after a reset.
wdreset[0-3]SignalslaveWatchdog timer reset signal.
wdresetreq[0-3]SignalmasterWatchdog timer IRQ outputs.

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