4.3.3. Parameters

Table 4.5 provides a description of the configuration parameters for the ARMCortexA9MPxnCT component. These parameters are set once, irrespective of the number of Cortex-A9 processors in your system. If you have multiple Cortex-A9 processors, then each processor has its own parameters.

Table 4.5. ARMCortexA9MPxnCT parameters

ParameterDescriptionTypeAllowed valueDefault value
CLUSTER_ID Processor cluster ID value.Integer0-150
CFGSDISABLEDisable some accesses to GIC registers.Booleantrue or falsefalse
FILTERENEnable filtering of accesses through pvbus_m0.Booleantrue or falsefalse
FILTERSTARTBase of region filtered to pvbus_m0.Integermust be aligned on 1MB boundary0x0
FILTERENDEnd of region filtered to pvbus_m0.Integermust be aligned on 1MB boundary0x0
PERIPHBASEBase address of peripheral memory space.Integer-0x13080000[a]
dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue or falsefalse
device-accurate-tlbSpecify whether all TLBs are modeled.Booleantrue or falsefalse[b]
dic-spi_countNumber of shared peripheral interrupts implemented.Integer0-223, in increments of 3264
icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue or falsefalse

[a] If you are using the ARMCortexA9MPxnCT component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.

[b] Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.


Table 4.6 provides a description of the configuration parameters for each ARMCortexA9MPxnCT component processor. These parameters are set individually for each processor you have in your system.

Table 4.6. ARMCortexA9MPxnCT individual processor parameters[2]

ParameterDescriptionTypeAllowed valueDefault value
CFGENDInitialize to BE8 endianness.Booleantrue or falsefalse
CFGNMFIEnable nonmaskable FIQ interrupts on startup.Booleantrue or falsefalse
CP15SDISABLEInitialize to disable access to some CP15 registers.Booleantrue or falsefalse
SMPnAMPSet whether the processor is part of a coherent domain.Booleantrue or falsefalse
TEINITT32 exception enable. The default has exceptions including reset handled in A32 state.Booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.Booleantrue or falsefalse
POWERCTLIDefault power control state for processor.Integer0-30
ase-present[a]Set whether the model has NEON support.Booleantrue or falsetrue
dcache-sizeSet D-cache size in bytes.Integer16KB, 32KB, or 64KB0x8000
icache-sizeSet I-cache size in bytes.Integer16KB, 32KB, or 64KB0x8000
min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-cmd_line[b]Command line available to semihosting SVC calls.Stringno limit except memory[empty string]
semihosting-enable

Enable semihosting SVC traps.

Caution

Applications that do not use semihosting must set this parameter to false.

Booleantrue or falsetrue
semihosting-ARM_SVCA32 SVC number for semihosting.Integer0x000000 - 0xFFFFFF0x123456
semihosting-Thumb_SVCT32 SVC number for semihosting.Integer0x00 - 0xFF0xAB
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F000000
vfp-enable_at_reset[c]Enable coprocessor access and VFP at reset.Booleantrue or falsefalse
vfp-present[a]Set whether model has VFP support.Booleantrue or falsetrue

[2] For the ARMCortexA9MPxnCT processors, the instance name for each processor consists of the normal instance name (in the provided examples, coretile.core) with a per processor suffix. For example the first processor in the example Cortex-A9MP platform has the instance name coretile.core.cpu0.

[a] The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A9 model. The options are:

vfp present and ase present

NEON and VFPv3-D32 supported.

vfp present and ase not present

VFPv3-D16 supported.

vfp not present and ase present

Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.

vfp not present and ase not present

Model has neither NEON nor VFPv3-D32 support.

[b] The value of argv[0] points to the first command line argument, not to the name of an image.

[c] This is a model specific behavior with no hardware equivalent.


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