4.5.1. Ports

Table 4.10 provides a brief description of the ports in the ARMCortexA8CT component. For more information, see the processor technical reference manual.

Table 4.10. ARMCortexA8CT ports

NamePort protocolTypeDescription
clk_inClockSignalslaveclock input
pvbus_mPVBusmastermaster port for all memory accesses
resetSignalslaveasynchronous reset signal input
irqSignalslaveasynchronous IRQ signal input
fiqSignalslaveasynchronous FIQ signal input
pmuirqSignalmasterperformance monitoring unit IRQ output
dmairqSignalmasternormal PreLoad Engine (PLE) interrupt output
dmasirqSignalmastersecure PLE interrupt output
dmaexterrirqSignalmasterPLE error interrupt output
ticksInstructionCountmasteroutput that can be connected to a visualization component
cfgend0Signalslaveinitialize to BE8 endianness after a reset
cfgnmfiSignalslaveenable nonmaskable FIQ interrupts after a reset
cfgteSignalslaveinitialize to take exceptions in T32 state after a reset
vinithiSignalslaveinitialize with high vectors enabled after a reset

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