4.5.3. Parameters

Table 4.11 provides a description of the configuration parameters for the ARMCortexA8CT component. For more information, see the processor technical reference manual.

Table 4.11. ARMCortexA8CT parameters

ParameterDescriptionTypeAllowed valueDefault value
CFGEND0Initialize to BE8 endianness.Booleantrue or falsefalse
CFGNMFIEnable nonmaskable FIQ interrupts on startup.Booleantrue or falsefalse
CFGTEInitialize to take exceptions in T32 state. Model starts in T32 state.Booleantrue or falsefalse
CP15SDISABLEInitialize to disable access to some CP15 registers.Booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.Booleantrue or falsefalse
l1_dcache-state_modelled[a]Include Level 1 data cache state model.Booleantrue or falsefalse
l1_icache-state_modelled[a]Include Level 1 instruction cache state model.Booleantrue or falsefalse
l2_cache-state_modelled[a]Include unified Level 2 cache state model.Booleantrue or falsefalse
l1_dcache-sizeSet L1 D-cache size in bytes.Integer16KB or32KB0x8000
l1_icache-sizeSet L1 I-cache size in bytes.Integer16KB or32KB0x8000
l2_cache-sizeSet L2 cache size in bytes.Integer128KB - 1024KB0x40000
device-accurate-tlbSpecify whether all TLBs are modeled.Booleantrue or falsefalse[b]
implements_vfpSet whether the model has been built with VFP and NEON support.Booleantrue or falsetrue
master_idmaster ID presented in bus transactionsInteger0x0000 - 0xFFFF0x0
min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-ARM_SVCA32 SVC number for semihosting.Integeruint24_t0x123456
semihosting-Thumb_SVCT32 SVC number for semihosting.Integeruint8_t0xAB
semihosting-cmd_line[c]Command line available to semihosting SVC calls.StringNo limit except memory[Empty string]
semihosting-enable

Enable semihosting SVC traps.

Caution

Applications that do not use semihosting must set this parameter to false.

Booleantrue or falsetrue
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F0000000
siliconIDValue as read by the system coprocessor siliconID register.Integeruint32_t0x41000000
vfp-enable_at_reset[d]Enable coprocessor access and VFP at reset.Booleantrue or falsefalse

[a] These three parameters permit you to define the cache state in your model. The default setting is for no caches. Any combination of true/false settings for the cache state parameters is valid. For example, if all three parameters are set to true, your model has L1 and L2 caches.

[b] Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.

[c] The value of argv[0] points to the first command line argument, not to the name of an image.

[d] This is a model specific behavior with no hardware equivalent.


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