4.6.3. Parameters

Table 4.13 provides a description of the configuration parameters for the ARMCortexA7xnCT component. These parameters are set once, irrespective of the number of Cortex-A7 processors in your system. If you have multiple Cortex-A7 processors, then each processor has its own configuration parameters, as shown in Table 4.14.

Table 4.13. ARMCortexA7xnCT parameters

ParameterDescriptionTypeAllowed ValueDefault Value
CFGSDISABLEDisable some accesses to GIC registers.Booleantrue or falsefalse
CLUSTER_IDProcessor cluster ID value.Integer0-150
PERIPHBASEBase address of peripheral memory space.Integer0x0000000000 - 0xFFFFFFFFFF0x13080000[a]
internal_vgicConfigures whether the model of the processor contains a VGIC.Booleantrue or falsetrue
dic-spi_countNumber of shared peripheral interrupts implemented.Integer0-480, in increments of 3264
l1_dcache-state_modelledSet whether L1 D-cache has stateful implementation.Booleantrue or falsefalse
l1_icache-state_modelledSet whether L1 I-cache has stateful implementation.Booleantrue or falsefalse
l2_cache-sizeSet L2 cache size in bytes.Integer0 (no L2 cache), 128KB, 256KB, 512KB, 1024KB0x800000
l2_cache-state_modelledSet whether L2 cache has stateful implementation.Booleantrue or falsefalse

[a] If you are using the ARMCortexA7xnCT component on a VE model platform, this parameter is set automatically to 0x2C000000 and is not visible in the parameter list.


Table 4.14 provides a description of the configuration parameters for each ARMCortexA7xnCT component processor. These parameters are set individually for each processor you have in your system.

Table 4.14. ARMCortexA7xnCT individual processor parameters

ParameterDescriptionTypeAllowed ValueDefault Value
CFGENDInitialize to BE8 endianness.Booleantrue or falsefalse
CP15SDISABLEInitialize to disable access to some CP15 registers.Booleantrue or falsefalse
DBGROMADDRThis value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address.Integer0x00000000 - 0xFFFFFFFF0x12000003
DBGROMADDRVIf true, this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid.Booleantrue or falsetrue
DBGSELFADDRThis value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address.Integer0x000100030x00010003
DBGSELFADDRVIf true, this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid.Booleantrue or falsetrue
TEINITT32 exception enable. The default has exceptions including reset handled in A32 state.Booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.Booleantrue or falsefalse
ase-present[a]Set whether CT model has been built with NEON™ support.Booleantrue or falsetrue
l1_dcache-sizeSize of L1 D-cache.Integer0x2000 - 0x100000x8000
l1_icache-sizeSize of L1 I-cache.Integer0x2000 - 0x100000x8000
min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-cmd_lineCommand line available to semihosting SVC calls.Stringno limit except memory[empty string]
semihosting-enable

Enable semihosting SVC traps.

Caution

Applications that do not use semihosting must set this parameter to false.

Booleantrue or falsetrue
semihosting-ARM_SVCA32 SVC number for semihosting.Integer0x000000 - 0xFFFFFF0x123456
semihosting-Thumb_SVCT32 SVC number for semihosting.Integer0x00 - 0xFF0xAB
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F000000
vfp-enable_at_reset[b]Enable coprocessor access and VFP at reset.Booleantrue or falsefalse
vfp-present[a]Set whether CT model has been built with VFP support.Booleantrue or falsetrue

[a] The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A7 model. The options are:

vfp present and ase present

NEON and VFPv4-D32 supported.

vfp present and ase not present

VFPv4-D16 supported.

vfp not present and ase present

Illegal. Forces vfp-present to true so model has NEON and VFPv4-D32 support.

vfp not present and ase not present

Model has neither NEON nor VFPv4-D32 support.

[b] This is a model-specific behavior with no hardware equivalent.


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