4.8.1. Ports

Table 4.18 provides a brief description of the ports in the ARMCortexA5CT component. For more information, see the processor technical reference manual.

Table 4.18. ARMCortexA5CT ports

NamePort protocolTypeDescription
cfgend[0]SignalslaveInitialize to BE8 endianness after a reset.
cfgnmfi[0]SignalslaveEnable nonmaskable FIQ interrupts after a reset.
clk_inClockSignalslaveMain processor clock input.
clusteridValueslaveValue read in MPIDR register.
cp15sdisable[0]SignalslaveDisable write access to some cp15 registers.
eventSignalpeerEvent input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
fiq[0]SignalslaveProcessor FIQ signal input.
irq[0]SignalslaveProcessor IRQ signal input.
pmuirq[0]SignalmasterPerformance Monitoring Unit (PMU) interrupt signal.
pvbus_m0PVBusmasterAXI master 0 bus master channel.
reset[0]SignalslaveProcessor reset signal.
standbywfe[0]SignalmasterIndicates if a processor is in WFE state.
standbywfi[0]SignalmasterIndicates if a processor is in WFI state.
teinit[0]SignalslaveInitialize to take exceptions in T32 state after a reset.
ticks[0]InstructionCountmasterProcessor instruction count for visualization.
vinithi[0]SignalslaveInitialize with high vectors enabled after a reset.

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