4.8.3. Parameters

Table 4.19 lists the parameters set at the processor level for the ARMCortexA5CT component.

Table 4.19. ARMCortexA5CT parameters

ParameterDescriptionTypeAllowed valueDefault value
CLUSTER_ID Processor cluster ID value.Integer0-150
device-accurate-tlbSpecify whether all TLBs are modeled.Booleantrue or falsefalse[a]
dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue or falsefalse
icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue or falsefalse

[a] Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.

Table 4.20 provides a description of the processor configuration parameters for the ARMCortexA5CT component.

Table 4.20. ARMCortexA5CT individual processor parameters

ParameterDescriptionTypeAllowed valueDefault value
CFGENDInitialize to BE8 endianness.Booleantrue or falsefalse
CFGNMFIEnable nonmaskable FIQ interrupts on startup.Booleantrue or falsefalse
CP15SDISABLEInitialize to disable access to some CP15 registers.Booleantrue or falsefalse
TEINITT32 exception enable. The default has exceptions including reset handled in A32 state.Booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.Booleantrue or falsefalse
POWERCTLIDefault power control state for processor.Integer0-30
ase-present[a]Set whether model has NEON support.Booleantrue or falsetrue
min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-cmd_lineCommand line available to semihosting SVC calls.Stringno limit except memory[empty string]

Enable semihosting SVC traps.


Applications that do not use semihosting must set this parameter to false.

Booleantrue or falsetrue
semihosting-ARM_SVCA32 SVC number for semihosting.Integer0x000000 - 0xFFFFFF0x123456
semihosting-Thumb_SVCT32 SVC number for semihosting.Integer0x00 - 0xFF0xAB
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F000000
vfp-enable_at_reset[b]Enable coprocessor access and VFP at reset.Booleantrue or falsefalse
vfp-present[a]Set whether the model has VFP support.Booleantrue or falsetrue
dcache-sizeSet D-cache size in bytes.Integer4KB, 8KB, 16KB, 32KB, or 64KB0x8000
icache-sizeSet I-cache size in bytes.Integer4KB, 8KB, 16KB, 32KB, or 64KB0x8000

[a] The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A5 model. The options are:

vfp present and ase present

NEON and VFPv3-D32 supported.

vfp present and ase not present

VFPv3-D16 supported.

vfp not present and ase present

Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.

vfp not present and ase not present

Model has neither NEON nor VFPv3-D32 support.

[b] This is a model specific behavior with no hardware equivalent.

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