4.9.1. Ports

Table 4.21 provides a brief description of the ports in the ARMCortexR7MPxnCT component. For more information, see the processor technical reference manual.

Table 4.21. ARMCortexR7MPxnCT ports

NamePort protocolTypeDescription
acp_sPVBusslaveSlave channel
cfgendSignalslaveInitialize to BE8 endianness after a reset.
cfgnmfiSignalslaveEnable nonmaskable FIQ interrupts after a reset.
clk_inClockSignalslaveMain processor clock input.
clusteridValueslaveValue read in MPIDR register.
dtcm[0-1]PVBusslavePort to allow external components to write to data TCM.
eventSignalpeerEvent input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
fiq[0-1]SignalslaveProcessor FIQ signal input.
fiqout[0-1]SignalmasterOutput of individual processor nFIQ from the interrupt controller.
fpuflags[0-1]ValueStatemasterFloating-point unit output flags.
initram[0-1]SignalslaveInitialize with ITCM enabled after reset.
ints[0-479]SignalslaveShared peripheral interrupts.
irq[0-1]SignalslaveProcessor IRQ signal input.
irqout[0-1]SignalmasterOutput of individual processor nIRQ from the interrupt controller.
itcm[0-1]PVBusslavePort to allow external components to write to instruction TCM.
periphbaseValueslaveBase of private peripheral region.
periphclk_inClockSignalslaveTimer/watchdog clock rate.
periphresetSignalslaveTimer and GIC reset signal.
pmuirq[0-1]SignalmasterPerformance Monitoring Unit (PMU) interrupt signal.
pmupriv[0-1]StateSignalmasterThis signal gives the status of the Cortex-R7 processor.
pvbus_m0PVBusmasterAXI master 0 bus master channel.
reset[0-1]SignalslaveIndividual processor reset signal.
scuevabortSignalmasterIndicates that an external abort has occurred during a coherency eviction.
scuresetSignalslaveSCU reset signal.
smpnamp[0-1]SignalmasterIndicates which processors are in SMP mode.
standbywfe[0-1]SignalmasterIndicates if a processor is in WFE state.
standbywfi[0-1]SignalmasterIndicates if a processor is in WFI state.
teinitSignalslaveInitialize to take exceptions in T32 state after a reset.
ticks[0-1]InstructionCountmasterProcessor instruction count for visualization.
vinithi[0-1]SignalslaveInitialize with high vectors enabled after a reset.
wdreset[0-1]SignalslaveWatchdog timer reset signal.
wdresetreq[0-1]SignalmasterWatchdog timer IRQ outputs.

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