4.9.3. Parameters

Table 4.22 provides a description of the configuration parameters for the ARMCortexR7MPxnCT component. These parameters are set once, irrespective of the number of Cortex-R7 processors in your system. If you have multiple Cortex-R7 processors, then each processor has its own parameters.

Table 4.22. ARMCortexR7MPxnCT parameters

ParameterDescriptionTypeAllowed valueDefault value
CLUSTER_ID Processor cluster ID value.Integer0x0 - 0xF0x0
LOCK_STEPAffects dual-processor configurations only, and ignored by single-processor configurations.Integer

0 - Disable. Set for two independent processors.

1 - Lock Step. Appears to the system as two processors but is internally modeled as a single processor.

3 - Split Lock. Appears to the system as two processors but can be statically configured from reset either as two independent processors or two locked processors. For the model, these are equivalent to Disable and Lock Step, respectively, except for the value of build options registers. The model does not support dynamically splitting and locking the processor.

MFILTERENEnables filtering of address ranges.Booleantrue or falsefalse
MFILTERENDSpecifies the end address for address filtering.Integer0x00000000 - 0xFFFFFFFF0x0
MFILTERSTARTSpecifies the start address for address filtering.Integer0x00000000 - 0xFFFFFFFF0x0
PERIPHBASEBase address of peripheral memory space.Integer0x00000000 - 0xFFFFFFFF0xAE100000[a]
dcache-state_modelledSet whether D-cache has stateful implementation.Booleantrue or falsefalse
ecc_onEnable Error Correcting Code.Booleantrue or falsefalse
dic-spi_countNumber of shared peripheral interrupts implemented.Integer0x0 - 0xE0x40
icache-state_modelledSet whether I-cache has stateful implementation.Booleantrue or falsefalse

[a] If you are using the ARMCortexR7MPxnCT component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.

Table 4.23 provides a description of the configuration parameters for each ARMCortexR7MPxnCT component processor. These parameters are set individually for each processor you have in your system.

Table 4.23. ARMCortexR7MPxnCT individual processor parameters[5]

ParameterDescriptionTypeAllowed valueDefault value
CFGENDInitialize to BE8 endianness.Booleantrue or falsefalse
CFGNMFIEnable nonmaskable FIQ interrupts on startup.Booleantrue or falsefalse
DP_FLOATSets whether double-precision instructions are available.Booleantrue or falsetrue
NUM_MPU_REGIONSets the number of MPU regions.Integer12-1616
POWERCTLIDefault power control state for processor.Integer0-30
SMPnAMPSet whether the processor is part of a coherent domain.Booleantrue or falsefalse
TEINITT32 exception enable. The default has exceptions including reset handled in A32 state.Booleantrue or falsefalse
VINITHIInitialize with high vectors enabled.Booleantrue or falsefalse
dcache-sizeSet D-cache size in bytes.Integer0x00000000 - 0x100000000x8000
icache-sizeSet I-cache size in bytes.Integer0x00000000 - 0x100000000x8000
min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-ARM_SVCA32 SVC number for semihosting.Integer0x000000 - 0xFFFFFF0x123456
semihosting-cmd_line[a]Command line available to semihosting SVC calls.Stringno limit except memory[empty string]

Enable semihosting SVC traps.


Applications that do not use semihosting must set this parameter to false.

Booleantrue or falsetrue
semihosting-heap_baseVirtual address of heap base.Integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.Integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.Integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-Thumb_SVCT32 SVC number for semihosting.Integer0x00 - 0xFF0xAB
tcm-presentDisables the DTCM and ITCM.Booleantrue or falsetrue
vfp-enable_at_reset[b]Enable coprocessor access and VFP at reset.Booleantrue or falsefalse
vfp-present[a]Set whether model has VFP support.Booleantrue or falsetrue

[5] For the ARMCortexR7MPxnCT processors, the instance name for each processor consists of the normal instance name (in the provided examples, coretile.core) with a per processor suffix. For example the first processor in the example Cortex-R7MP platform has the instance name coretile.core.cpu0.

[a] The value of argv[0] points to the first command line argument, not to the name of an image.

[b] This is a model specific behavior with no hardware equivalent.

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