4.10.1. Ports

Table 4.24 provides a brief description of the ports in the ARMCortexR5CT component. For more information, see the processor technical reference manual.

Table 4.24. ARMCortexR5CT ports

Name

Port Protocol

Type

Description

acp_s

PVBus

Slave

ACP slave port.

cfgatcmsz[2]

Value

Slave

ATCM size.

cfgbtcmsz[2]

Value

Slave

BTCM size.

cfgend[2]

Signal

Slave

This signal is for EE bit initialization.

cfgnmfi[2]

Signal

Slave

Controls nonmaskable FIQ interrupts.

clk_in

ClockSignal

Slave

The clock signal connected to the clk_in port is used to determine the rate at which the processor executes instructions.

event[2]

Signal

Peer

This peer port of event input (and output) is for wakeup from WFE.

fiq[2]

Signal

Slave

This signal drives the FIQ interrupt handling of the processor.

groupid

Value

Slave

Group ID used for MPIDR.

initrama[2]

Signal

Slave

If ATCM is enabled at reset.

initramb[2]

Signal

Slave

If BTCM is enabled at reset.

irq[2]

Signal

Slave

This signal drives the interrupt handling of the processor.

loczrama[2]

Signal

Slave

Location of ATCM at reset.

pmuirq[2]

Signal

Master

Interrupt signal from performance monitoring unit.

pvbus_m

PVBus

Master

The processor generates bus requests on this port.

reset[2]

Signal

Slave

Raising this signal puts the processor into reset mode.

slresetSignalSlave

Split lock signal. Contact ARM for details.

slsplitSignalSlave

Split lock signal. Contact ARM for details.

standbywfe[2]

Signal

Master

This signal indicates if a processor is in wfe state.

standbywfi[2]

Signal

Master

This signal indicates if a processor is in WFI state.

teinit[2]

Signal

Slave

Default exception handling state.

ticks[2]

InstructionCount

Master

Connect this port to one of the two ticks ports on a visualization component to display a running instruction count.

vic_ack[2]

Signal

Master

Vic acknowledge port to primary VIC.

vic_addr[2]

ValueState

Slave

Vic address port from primary VIC.

vinithi

Signal

Slave

This signal controls the location of the exception vectors at reset.


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