4.10.3. Parameters

Table 4.25 provides a description of the configuration parameters for the ARMCortexR5CT component. These parameters are set once, irrespective of the number of Cortex-R5 processors in your system. If you have multiple Cortex-R5 processors, then each processor has its own parameters.

Table 4.25. ARMCortexR5CT parameters

Parameter

Description

Type

Allowed Value

Default Value

GROUP_ID

Value read in GROUP ID register field, bits[15:8] of the MPIDR.

Integer

0-15

0

INST_ENDIAN

Controls whether the model supports the instruction endianness bit. For more information, see the ARM Architecture Reference Manuals.

Boolean

true or falsetrue
LOCK_STEP

Affects dual-processor configurations only, and ignored by single-processor configurations.

Integer

0 - Disable. Set for two independent processors.

1 - Lock Step. Appears to the system as two processors but is internally modeled as a single processor.

3 - Split Lock. Appears to the system as two processors but can be statically configured from reset either as two independent processors or two locked processors. For the model, these are equivalent to Disable and Lock Step, respectively, except for the value of build options registers. The model does not support dynamically splitting and locking the processor.

0

MICRO_SCU

Controls whether the effects of the MicroSCU are modeled. For more information, see the Cortex-R5 and Cortex-R5F Technical Reference Manual.

Boolean

true or falsetrue
NUM_BREAKPOINTS

Controls with how many breakpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled.

Integer

2-8

3

NUM_WATCHPOINTS

Controls with how many watchpoint pairs the model has been configured. This only affects the build options registers, because debug is not modeled.

Integer

1-8

2

SLSPLIT

Sets whether the model starts in split mode or locked mode. Contact ARM for details.

Boolean

true or false.

If True, model starts up in split mode.

If False, model starts up in locked mode.

This only has an effect if the LOCK_STEP parameter is set to 3.

false

dcache-state_modelled

Set whether D-cache has stateful implementation.

Boolean

true or falsefalse
icache-state_modelled

Set whether I-cache has stateful implementation.

Boolean

true or falsefalse

Table 4.26 provides a description of the configuration parameters for each ARMCortexR5MPxnCT component processor. These parameters are set individually for each processor you have in your system.

Table 4.26. ARMCortexR5CT individual processor parameters

Parameter

Description

Type

Allowed Value

Default Value

CFGATCMSZ

Sets the size of the ATCM.

Integer

0x00000000 - 0xE

0xE

CFGBTCMSZ

Sets the size of the BTCM.

Integer

0x00000000 - 0xE

0xE

CFGEND

Initialize to BE8 endianness.

Boolean

true or falsefalse
CFGIE

Set the reset value of the instruction endian bit.

Boolean

true or falsefalse
CFGNMFI

Enable nonmaskable FIQ interrupts on startup.

Boolean

true or falsefalse
DP_FLOAT

Sets whether double-precision instructions are available. For more information, see the ARM Architecture Reference Manuals.

Boolean

true or false.

If True, then double precision VFP is supported.

If False, then the VFP is single precision only.

true

NUM_MPU_REGION

Sets the number of MPU regions.

Integer

0x00, 0xC, 0x10.

0 = no MPU.

0xC

TEINIT

T32 exception enable. The default has exceptions including reset handled in A32 state.

Boolean

true or falsefalse
VINITHI

Initialize with high vectors enabled.

Boolean

true or falsefalse
atcm_base[a]

Model-specific. Sets the base address of the ATCM. For more information about the processor configuration signals, see the Cortex-R5 and Cortex-R5F Technical Reference Manual.

Integer

0x00000000 - 0xFFFFFFFF

0x40000000

btcm_base[a]

Model-specific. Sets the base address of the BTCM. For more information about the processor configuration signals, see the Cortex-R5 and Cortex-R5F Technical Reference Manual.

Integer

0x00000000 - 0xFFFFFFFF

0x00000000

dcache-size

Set D-cache size in bytes.

Integer

0x1000 - 0x10000

0x10000

icache-size

Set I-cache size in bytes.

Integer

0x1000 - 0x10000

0x10000

min_sync_levelControls the minimum syncLevel.Integer0-30
semihosting-ARM_SVC

A32 SVC number for semihosting.

Integer

0x000000 - 0xFFFFFF

0x123456

semihosting-cmd_line

Command line available to semihosting SVC calls.

String

No limit except memory

[Empty string]

semihosting-enable

Enable semihosting SVC traps.

Caution

Applications that do not use semihosting must set this parameter to False.

Boolean

true or falsetrue
semihosting-heap_base

Virtual address of heap base.

Integer

0x00000000 - 0xFFFFFFFF

0x0

semihosting-heap_limit

Virtual address of top of heap.

Integer

0x00000000 - 0xFFFFFFFF

0x0F000000

semihosting-stack_base

Virtual address of base of descending stack.

Integer

0x00000000 - 0xFFFFFFFF

0x10000000

semihosting-stack_limit

Virtual address of stack limit.

Integer

0x00000000 - 0xFFFFFFFF

0x0F000000

semihosting-Thumb_SVC

T32 SVC number for semihosting.

Integer

0x00 - 0xFF

0xAB

vfp-enable_at_reset[a]

Enable coprocessor access and VFP at reset.

Boolean

true or falsefalse
vfp-present

Set whether model has VFP support.

Boolean

true or falsetrue

[a] This is a model-specific behavior with no hardware equivalent.


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