4.10.6. Debug Features

The ARMCortexR5CT component exports a CADI debug interface.


All Core, VFP and CP15 registers, apart from performance counter registers, are visible in the debugger. See the processor technical reference manual for a detailed description of available registers.

The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register has no defined behavior.


There is direct support for:

  • single address unconditional instruction breakpoints

  • unconditional instruction address range breakpoints

  • single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The current models support processor exception breakpoints by the use of pseudoregisters available in the debugger register window. When debugger support is added to directly support processor exceptions, these pseudoregisters are removed.

Setting an exception register to a nonzero value cause execution to stop on entry to the associated exception vector.


The ARMCortexR5CT component presents a single 4GB view of memory.

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