4.11.1. Ports

Table 4.27 provides a brief description of the ports in the ARMCortexR4CT component. For more information, see the processor technical reference manual.

Table 4.27. ARMCortexR4CT ports

NamePort protocolTypeDescription
clk_inClockSignalslaveclock input
pvbus_mPVBusmastermaster port for all memory accesses
resetSignalslaveasynchronous reset signal input
irqSignalslaveasynchronous IRQ signal input
fiqSignalslaveasynchronous FIQ signal input
pmuirqSignalmasterperformance monitoring unit IRQ output
vic_addrValueStateslaveaddress input for connection to PL192 VIC
vic_ackSignalmasteracknowledge signal output for PL192 VIC
cfgie[a]Signalslaveconfigure instruction endianness after a reset
ticksInstructionCountmasteroutput that can be connected to a visualization component
cfgend0Signalslaveinitialize to BE8 endianness after a reset
cfgnmfiSignalslaveenable nonmaskable FIQ interrupts after a reset
cfgteSignalslaveinitialize to take exceptions in T32 state after a reset
vinithiSignalslaveinitialize with high vectors enabled after a reset
standbywfiSignalmastersignal that the processor is in standby waiting for interrupts
initramiSignalslaveinitialize with ITCM enabled after reset
initramdSignalslaveinitialize with DTCM enabled after reset
itcmPVBusslaveslave access to ITCM
dtcmPVBusslaveslave access to DTCM

[a] This is implemented in the model, although it is optional in hardware.


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