4.11.6. Debug features

The ARMCortexR4CT component exports a CADI debug interface.

Registers

All processor and CP15 registers are visible in the debugger. See the processor technical reference manual for a detailed description of available registers.

The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register has no defined behavior.

Breakpoints

There is direct support for:

  • single address unconditional instruction breakpoints

  • unconditional instruction address range breakpoints

  • single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The current models support processor exception breakpoints by pseudoregisters that are available in the debugger register window. When debugger support is added to directly support processor exceptions, the pseudoregisters are removed.

Setting an exception register to a nonzero value causes execution to stop on entry to the associated exception vector.

Memory

The ARMCortexR4CT component presents one 4GB view of virtual memory.

Copyright © 2008-2013 ARM. All rights reserved.ARM DUI 0423O
Non-ConfidentialID060613