4.12.1. Ports

Table 4.29 provides a brief description of the ports in the ARMCortexM4CT component. For more information, see the processor technical reference manual.

Table 4.29. ARMCortexM4CT ports

NamePort protocolTypeDescription
auxfaultValueslaveauxiliary fault status information
bigendSignalslaveconfigure endianness after a reset
clk_inClockSignalslaveclock input
currpriValuemasterindicates the current execution priority of the processor
edbgrqSignalmasterexternal debug request
eventSignalpeerevent input and output for wakeup from WFE. This port combines the TXEV and RXEVsignals
intisr[0-239]Signalslaveexternal interrupt signals
intnmiSignalslavenonmaskable interrupt
lockupSignalmasterasserted when processor is in lockup state
poresetSignalslaveasynchronous power-on reset signal input
pvbus_mPVBusmastermaster port for all memory accesses except those on the External Private Peripheral Bus
pv_ppbus_mPVBusmastermaster port for memory accesses on the External Private Peripheral Bus
resetSignalslaveasynchronous reset signal input (not debug components)
sleepdeepSignalmasterindicates that the processor is in deep sleep
sleepingSignalmasterindicates that the processor is in sleep
stcalibValueslaveSysTick calibration value
stclkClockSignalslavereference clock input for SysTick
sysresetSignalslaveasynchronous reset signal input
sysresetreqSignalmastersystem reset request
ticksInstructionCountmasteroutput that can be connected to a visualization component
dbgen[a]Signalslaveenable hardware debugger access
fpudisableSignalslavedisable FPU on next reset
mpudisableSignalslavedisable MPU on next reset
fpxxcValuemastercumulative exception flags from the Floating Point Status and Control Register (FPSCR). This value port combines the five RTL signals FPIXC, FPIDC, FPOFC, FPUFC, FPDZC and FPIOC.

[a] Since the CT model does not provide a DAP port or halting debug capability, this signal is ignored.

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