4.14.1. Ports

Table 4.33 provides a brief description of the ports in the ARMAEMv7AMPCT model.

Table 4.33. ARMAEMv7AMPCT ports

NamePort ProtocolTypeDescription
acp_sPVBusslaveAXI ACP slave port
cfgend[0-3]SignalslaveInitialize to BE8 endianness after a reset.
cfgnmfi[0-3]SignalslaveDisables FIQ mask in Current Program Status Register (CPSR).
cfgsdisableSignalslaveDisable write access to some GIC registers.
cfgteSignalslaveInitializes to take exceptions in T32 state after a reset.
clk_inClockSignalslaveMain processor clock input.
clusteridValueslaveSets the value in the CLUSTERID field (bits[11:8]) of the MPIDR.
coreporeset[0-3]SignalslaveIndividual processor reset signal.
cp15sdisable[0-3]SignalslaveDisable write access to some secure cp15 registers.
dmairqSignalmasterInterrupt signal from L1 DMA.
dmasirqSignalmasterSecure interrupt signal from L1 DMA.
eventSignalpeerEvent input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
filterenSignalslaveEnables filtering of address ranges between master bus ports.
filterendValueslaveSets end of region mapped to pvbus_m1.
filterstartValueslaveSets start of region mapped to pvbus_m1
fiq[0-3]SignalslaveProcessor FIQ signal input.
hyp_timer_event[0-3]SignalmasterInterface to SoC level counter module.
initramSignalslaveInitializes with ITCM enabled after reset.
ints[0-223]SignalslaveDrives the interrupt port of the GIC.
irq[0-3]SignalslaveProcessor IRQ signal input.
periphbaseValueslaveBase of private peripheral region.
periphclk_inClockSignalslaveTimer/watchdog clock rate.
periphresetSignalslaveResets the timer and interrupt controller.
phy_timer_ns_event[0-3]SignalmasterInterface to SoC level counter module.
phy_timer_s_event[0-3]SignalmasterInterface to SoC level counter module.
pmuirq[0-3]SignalmasterPerformance Monitoring Unit (PMU) interrupt signal.
presetdbg[0-3]SignalslaveIndividual processor reset signal.
pvbus_m0PVBusmasterAXI master 0 bus master channel.
pvbus_m1PVBusmasterAXI master 1 bus master channel.
pwrctli[0-3]ValueslaveResets the reset value for SCU processor status register.
pwrctlo[0-3]ValuemasterSends SCU processor status register bits.
reset[0-3]SignalslaveIndividual processor reset signal.
scuresetSignalslaveResets SCU.
smpnamp[0-3]SignalmasterIndicates AMP or SMP mode for each processor.
standbywfe[0-3]SignalmasterIndicates if a processor is in WFE state.
standbywfi[0-3]SignalmasterIndicates if a processor is in WFI state.
sysporesetSignalslaveIndividual processor reset signal.
teinit[0-3]SignalslaveInitialize to take exceptions in T32 state after a reset.
ticks[0-3]InstructionCountmasterProcessor instruction count for visualization.
vfiq[0-3]SignalslaveProcessor virtual FIQ signal input.
vic_ackSignalmasterAcknowledge port to primary VIC.
vic_addrValueStateslaveAddress port from primary VIC.
vinithi[0-3]SignalslaveInitialize with high vectors enabled after a reset.
virq[0-3]SignalslaveProcessor virtual IRQ signal input.
virt_timer_event[0-3]SignalmasterInterface to SoC level counter module.
wdreset[0-3]SignalslaveResets individual watchdog.
wdresetreq[0-3]SignalmasterResets rest of the Cortex-A9 MP system.

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