4.14.6. Debug Features

The ARMAEMv7AMPCT model exports a CADI debug interface.

Registers

All processor, VFP, CP14 and CP15 registers, apart from performance counter registers, are visible in the debugger.

Breakpoints

There is direct support for:

  • single address unconditional instruction breakpoints

  • unconditional instruction address range breakpoints

  • single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The current models support processor exception breakpoints by the use of pseudoregisters available in the debugger register window. When debugger support is added to directly support processor exceptions, these pseudoregisters are removed.

Setting an exception register to a nonzero value causes execution to stop on entry to the associated exception vector.

Memory

The Secure and Normal views show the contents of memory that are read by the processor when it performs a data-side memory access in the secure and non-secure modes in TrustZone. The Level 1 cache is examined first, and in the case of a cache miss the Level 2 cache, if present, is examined. This continues until external memory or peripherals are examined. This view is indexed by modified virtual address.

The L1-DCache, L1-DCacheNS, L2-DCache, ... views show the contents of an individual cache block. If there is a cache miss at this level, no data is shown. These views cause no side-effects in the simulation. This view is indexed by physical address.

The External and ExternalNS views show the contents of memory available from the external bus interface of the processor. Memory is shown only if it can be read without causing side effects. In most cases, the contents of the RAM are available but peripheral registers are not. Availability of non-idempotent memory such as flash units might depend on the state of the flash unit and code that has already been executed in the model. This view is indexed by physical address.

TLB

Each active processor in the multiprocessor exports a CADI interface that describes the current contents of its TLB.

Note

This view is subject to change in future versions.

You can examine TLB entries by opening a Disassembly view in the debugger window for the TLB CADI interface. You can select two display modes from the Memory Space menus:

Entries by index

The Address field is an index into a linear, ordered list of TLB entries.

All entries in the TLB are shown, regardless of security state or ASID. Entries outside the current state, or that do not match the current ASID, are not be used by the processor for physical address translations.

This view is available only for TLBs with a limited, finite size. It is not supported when the tlb_prefetch option is enabled, because there is no linear indexing of TLB entries in the infinite pre-fetching TLB model.

Entries by MVA

The Address field corresponds to the Modified Virtual Address (MVA) from which a TLB entry is translated.

This view is specific to a particular security state and ASID. You can control this by opening a Register view in the debugger window. You can change the registers NS and ASID to view the corresponding TLB entries.

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