clk_in | ClockSignal | slave | clock input |
pvbus_m | PVBus | master | master port for all memory accesses |
reset | Signal | slave | asynchronous reset signal input |
irq | Signal | slave | asynchronous IRQ signal input |
fiq | Signal | slave | asynchronous FIQ signal input |
pmuirq | Signal | master | performance monitoring unit IRQ output |
dmairq | Signal | master | normal DMA interrupt output |
dmasirq | Signal | master | secure DMA interrupt output |
dmaexterrirq | Signal | master | DMA error interrupt output |
vic_addr | ValueState | slave | address input for connection to PL192 VIC |
vic_ack | Signal | master | acknowledge signal output for PL192 VIC |
ticks | InstructionCount | master | output that can be connected to a visualization component |