4.16.1. Ports

Table 4.46 provides a brief description of the ports of the ARM1136CT component. For more information, see the processor technical reference manual.

Table 4.46. ARM1136CT ports

NamePort protocolTypeDescription
clk_inClockSignalslaveclock input
pvbus_mPVBusmastermaster port for all memory accesses
resetSignalslaveasynchronous reset signal input
irqSignalslaveasynchronous IRQ signal input
fiqSignalslaveasynchronous FIQ signal input
pmuirqSignalmasterperformance monitoring unit IRQ output
dmasirq[a]Signalmasternormal DMA interrupt output
vic_addrValueStateslaveaddress input for connection to PL192 VIC
vic_ackSignalmasteracknowledge signal output for PL192 VIC
ticksInstructionCountmasteroutput that can be connected to a visualization component

[a] This signal is currently misnamed and is to be named dmairq.


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